Method and apparatus for scan chain data management
Processing logic circuit has State Retention Power Gating logic circuit including at least two scan chains having different lengths and operable to collect state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state into a second, different, state. The processing logic circuit includes a memory operable to store collected state information about the at least a portion of the processing logic circuit, and logic circuit operable to rearrange the collected state information data for scan chains shorter than a longest scan chain, to enable valid return of the collected state information data, for the scan chains shorter than a longest scan chain, to the at least a portion of the processing logic circuit when the at least a portion of the processing logic circuit returns to the first state.
1. Processing logic circuit for use in a computing system, wherein the processing logic circuit has a State Retention Power Gating logic circuit having at least two scan chains having different lengths and operable to collect state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state into a second, different, state, said processing logic circuit comprising:
a memory coupled to the State Retention Power Gating logic circuit and operable to store a collected state information about the at least a portion of the processing logic circuit; and
a further logic circuit coupled to the memory and operable to rearrange the collected state information data for scan chains shorter than a longest scan chain within the at least a portion of the processing logic circuit, to enable valid return of the collected state information data, for the scan chains shorter than a longest scan chain, to the at least a portion of the processing logic circuit when the at least a portion of the processing logic circuit returns to the first state.
2. The processing logic circuit of claim 1 , wherein the second, different, state is a state in which the at least a portion of the processing logic circuit is in a different context or is in a lower power state.
3. The processing logic circuit of claim 1 , wherein the further logic circuit coupled to the memory comprises a processing unit within a same or another portion of the processing logic circuit that is to be placed into the second, different, state.
4. The processing logic circuit of claim 3 , wherein the processing unit is a central processing unit, CPU, within the processing logic circuit.
5. The processing logic circuit of claim 1 , wherein to rearrange the collected state data for scan chains shorter than the longest scan chain comprises moving invalid state data collected during a SRPG state data storing process from one end of the data structure comprising the state data to another end of the data structure.
6. The processing logic circuit of claim 1 , wherein the collected state information data is stored in a FIFO memory data structure and the stored collected state information data is rearranged by placing invalid state information data for a shorter scan chain at an end of the FIFO memory that is loaded first back into the at least a portion of the processing logic circuit.
7. The processing logic circuit of claim 1 , wherein the processing logic circuit is a processor for a computing system or a System on Chip.
8. The processing logic circuit of claim 1 , wherein the memory coupled to the State Retention Power Gating logic circuit is part of the at least a portion of the processing logic circuit to be placed from a first state into a second different state, and the processing logic circuit further comprises further logic circuit to reset the at least a portion of the processing logic circuit containing the memory.
9. The processing logic circuit of claim 1 , wherein the at least a portion of the processing logic circuit comprises any SRPG enabled modules or portions of the processing logic circuit.
10. A method of scan chain data management in processing logic circuit, wherein the processing logic circuit has State Retention Power Gating logic circuit having at least two scan chains having different lengths and operable to collect state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state into a second, different, state, said method comprising:
collecting state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state to a second, different, state; and
rearranging the collected state information data for the scan chains shorter than a longest scan chain, to enable valid return of the collected state information data for the shorter scan chains to the at least a portion of the processing logic circuit when the at least a portion of the processing logic circuit returns to the first state.
11. The method of claim 10 , wherein the second, different, state is a state in which the at least a portion of the processing logic circuit is in a different context or is in a lower power state.
12. The method of claim 10 , further comprising using a processing unit within a same or another portion of the processing logic circuit that is to be placed into the second, different, state.
13. The method of claim 12 , further comprising using a processing unit that is a main central processing unit, CPU, or another CPU within the processing logic circuit.
14. The method of claim 10 , wherein rearranging the collected state data for scan chains shorter than the longest scan chain comprises moving invalid data collected during a SRPG state data storing process from one end of the data structure comprising the state data to another end of the data structure.
15. The method of claim 10 further comprising storing the collected state information data in a FIFO memory data structure and rearranging the stored collected state information data by placing invalid state information data for a shorter scan chain at an end of the FIFO memory that is loaded first back into the at least a portion of the processing logic circuit.
16. The method of claim 10 , further comprising collecting state information using a memory coupled to the State Retention Power Gating logic circuit that is part of the at least a portion of the processing logic circuit to be placed from a first state into a second different state; and
resetting the at least a portion of the processing logic circuit prior to or at a same time as rearranging the data.
17. The method of claim 10 , further comprising applying the method to any SRPG enabled modules or portions of the processing logic circuit.