A METHOD AND APPARATUS FOR USING A CPU CACHE MEMORY FOR NON-CPU RELATED TASKS
There is provided a processor for use in a computing system, said processor including at least one Central Processing Unit (CPU), a cache memory coupled to the at least one CPU, and a control unit coupled to the cache memory and arranged to obscure the existing data in the CPU cache memory, and assign control of the CPU cache memory to at least one other entity within the computing system. There is also provided a method of using a CPU cache memory for non-CPU related tasks in a computing system.
1 . A processor for use in a computing system, said processor comprising:
at least one Central Processing Unit (CPU);
a cache memory coupled to the at least one CPU; and
a control unit coupled to the cache memory and arranged to:
obscure the existing data in the CPU cache memory, and
assign control of the CPU cache memory to at least one other entity within the computing system.
2 . The processor of claim 1 , wherein the control unit is arranged to obscure the existing data in the cache memory by being arranged to render the existing data inoperative or unreadable to the at least one other entity within the computing system once that entity has control of the CPU cache memory.
3 . The processor of claim 1 , wherein the control unit is arranged to obscure the existing data in the cache memory by being arranged to:
overwrite at least a portion of the existing data within the CPU cache memory, or
delete at least a portion of the existing data within the CPU cache memory.
4 . The processor of claim 3 , wherein the at least a portion of the existing data comprises all of the existing data within the CPU cache memory.
5 . The processor of claim 1 , wherein assignment of control of the CPU cache memory to the at least one other entity within the computing system further comprises providing the at least one other entity within the computing system at least one of read access or write access to the CPU cache memory, wherein the control unit is further arranged to provide said at least one of read access or write access to the CPU cache memory to the at least one other entity in the computing system.
6 . The processor of claim 1 , wherein an obscuring of the data and an assignment of control of the CPU cache occurs in response to at least one of a request for access to the CPU cache by the at least one other entity or as a result of the CPU entering a lower power state.
7 . The processor of claim 1 , wherein the control unit is a cache controller or a DMA unit.
8 . The processor of claim 5 , wherein the at least one of read access or write access is at least one of time limited or revocable, dependent on a need of the CPU unit to access the CPU cache memory.
9 . The processor of claim 1 , wherein the processor is a system on chip multimedia applications processor having at least one main CPU and at least one other CPU, and wherein the at least one other CPU is one of the at least one other entity within the computing system.
10 . The processor of claim 1 , wherein the CPU cache memory is arranged to be used by the at least one other entity within the computing system as a multimedia buffer memory.
11 . A method of using a CPU cache memory for non-CPU related tasks in a computing system comprising:
obscuring existing data in the CPU cache memory; and
assigning control of the CPU cache memory to at least one other entity within the computing system.
12 . The method of claim 10 , wherein obscuring existing data in the CPU cache memory comprises rendering the existing data inoperative or unreadable to the at least one other entity within the computing system once that entity has control of the CPU cache memory.
13 . The method of claim 10 , wherein obscuring existing data in the CPU cache memory comprises one or more of:
overwriting at least a portion of the existing data; or
deleting at least a portion of the existing data.
14 . The method of claim 10 , further comprising flushing the cache prior to allowing access to the cache by at least one other entity within the computing system
15 . The method of claim 10 , wherein assigning control of the CPU cache memory to at least one other entity within the computing system comprises providing at least one of read access or write access to the CPU cache memory by the at least one other entity within the computing system.
16 . The method of claim 15 , wherein the at least one of read access or write access is at least one of time limited or revocable, dependent upon a need of the CPU unit to access the CPU cache memory.
17 . The method of claim 10 , wherein providing the at least one of read access or write access to the cache memory comprises providing a Direct Memory Access to the cache.
18 . The method of claim 10 , wherein assigning control of the CPU cache memory to another entity within the computing system is carried out in order to provide a temporary multimedia buffer memory.
19 . The processor of claim 1 , wherein the CPU cache memory is a level 2 or level 3 cache memory on the same semiconductor die as the CPU.
20 . (canceled)