IP Library › Granted Patent US 10,826,982
Granted Patent B2
US 10,826,982 · App. 14/655,168 · Granted Nov 3, 2020

Packet processing architecture and method therefor

Inventors: Stefania Gandal (Hertzelia, IL); Noam Efrati (Beer Sheva, IL); Adi Katz (Ramat Gan, IL)
Assignee: NXP USA, Inc.
H04L67/104H04L49/1546H04L69/321
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Quick Facts
Patent No.
US 10,826,982
App. No.
14/655,168
Granted
Nov 3, 2020
Kind
B2
Abstract

A packet processing architecture includes a plurality of packet processing stages, wherein at least one of the packet processing stages includes multiple next processing stage modules that are operably coupled to respective further processing stages, wherein the multiple next processing stage modules are dynamically configurable.

Claims (13)

1. A packet processing architecture comprising a plurality of packet processing stages arranged in series to form a pipeline for processing packets, wherein at least one of the packet processing stages comprises multiple next processing stage modules that are operably coupled to respective further packet processing stages, wherein the at least one of the packet processing stages comprises a first next processing stage register and a second next processing stage register, the first next processing stage register and the second next processing stage register connected to different packet processing stages of the plurality of packet processing stages, and wherein the at least one of the packet processing stages dynamically evaluates which one of the first and second next processing stage registers should be utilised by processing a received data packet to determine content of the received data packet and performing a stateful examination of the content, and selects one of the first and second next processing stage registers for utilization based on the processing.

2. The packet processing architecture of claim 1 wherein the at least one of the packet processing stages is arranged to dynamically configure at least one of the first next processing stage register and the second next processing stage register in response to processing the received data packet.

3. The packet processing architecture of claim 1 wherein the at least one of the packet processing stages is arranged to process the received data packet passing there through to determine a packet processing stage of the received data packet.

4. The packet processing architecture of claim 1 wherein the at least one of the multiple next processing stage modules is arranged to feedback a received data packet to one or more previous packet processing stages of the plurality of packet processing stages.

5. The packet processing architecture of claim 4 wherein the at least one of the multiple next processing stage modules forms a repeat feedback loop between packet processing stages of the plurality of packet processing stages.

6. The packet processing architecture of claim 1 wherein the at least one of the multiple next processing stage modules is arranged to bypass one or more packet processing stages of the plurality of packet processing stages.

7. A method for a packet processing architecture comprising a plurality of packet processing stages arranged in series to form a pipeline for processing packets, wherein at least one of the packet processing stages comprises multiple next processing stage modules, a first next processing stage register and a second next processing stage register, the first next processing stage register and the second next processing stage register connected to different packet processing stages of the plurality of packet processing stages, the method comprising:

the at least one of the packet processing stages dynamically evaluating which of the first and second next processing stage registers should be utilised by processing a received data packet to determine content of the received data packet, and selecting one of the first and second next processing stage registers for utilization based on the content.

8. The method of claim 7 , further comprising dynamically configuring at least one of the first next processing stage register and the second next processing stage register in response to processing the received data packet.

9. The method of claim 7 wherein processing the received data packet passing through comprises determining a processing stage of the received data packet.

10. The method of claim 7 further comprising feeding back a received data packet to one or more previous packet processing stages of the plurality of packet processing stages.

11. The method of claim 7 further comprising forming a repeat feedback loop between packet processing stages of the plurality of packet processing stages.

12. The method of claim 7 further comprising bypassing one or more packet processing stages of the plurality of packet processing stages.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 20, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037565/0527 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 20, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037565/0510 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0859 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 6, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 036284/0105 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 6, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 036284/0339 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 6, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 036284/0363 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2015
From: GANDAL, STEFANIA; EFRATI, NOAM; KATZ, ADI
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 036012/0493 →
Continuity (1)
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