Graphene devices with local dual gates

1. An electronic device comprising:

an insulator;

a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator;

a first dielectric layer formed over the first gate and insulator;

a channel comprising a bilayer graphene layer formed on the first dielectric layer, wherein the first dielectric layer provides a substantially flat surface on which the channel is formed;

a second dielectric layer formed over the bilayer graphene layer, wherein the bilayer graphene layer provides a substantially flat surface on which the second dielectric layer is formed; and

a local second gate formed over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer;

wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and

wherein the local first gate is controllable independent of the local second gate.

2. The device of claim 1 , further comprising:

source and drain regions that are connected by the channel; and

a contact formed on each of the source and drain regions.

3. The device of claim 1 , wherein the first pair of gates operates as gates of a first transistor.

4. The device of claim 3 , further comprising:

a local third gate embedded in the insulator with a top surface of the third gate being substantially coplanar with a surface of the insulator; and

a local fourth gate formed over the second dielectric layer, each of the local third and fourth gates configured to be capacitively coupled to the channel of the bilayer graphene layer;

wherein the local third and fourth gates form at least a second pair of gates to locally control at least a second portion of the bilayer graphene layer;

wherein the at least second pair of gates operates as gates of a second transistor; and

wherein the local third gate is controllable independent of the local fourth gate.

5. The device of claim 4 , wherein at least one of the local first, second, third and fourth gates comprises metal material.

6. The device of claim 4 , wherein at least one of the local first, second, third and fourth gates having a channel length of approximately one (1) nm to approximately one (1) μm.

7. The device of claim 4 , wherein at least one of the local first, second, third and fourth gates comprises poly-silicon.

8. The device of claim 4 , wherein the first transistor having a threshold voltage that is determined by the local first and second gates.

9. The device of claim 4 , wherein the at least second transistor having a threshold voltage that is determined by the local third and fourth gates.

10. The device of claim 1 , wherein at least one of the first and second dielectric layers comprises one or more of aluminum oxide and hafnium oxide.

11. The device of claim 1 , wherein the insulator comprises silicon dioxide.

12. An integrated circuit including at least one dual gate graphene device circuit, the at least one device circuit comprising:

an insulator;

a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator;

a first dielectric layer formed over the first gate and insulator;

a channel comprising a bilayer graphene layer formed on the first dielectric layer, wherein the first dielectric layer provides a substantially flat surface on which the channel is formed;

a second dielectric layer formed over the bilayer graphene layer, wherein the bilayer graphene layer provides a substantially flat surface on which the second dielectric layer is formed; and

a local second gate formed over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer;

wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and

wherein the local first gate is controllable independent of the local second gate.

13. The integrated circuit of claim 12 , further comprising:

source and drain regions that are connected by the channel; and

a contact formed on each of the source and drain regions.

14. The integrated circuit of claim 12 , wherein the first pair of gates operates as gates of a first transistor.

15. The integrated circuit of claim 14 , further comprising:

a local third gate embedded in the insulator with a top surface of the third gate being substantially coplanar with a surface of the insulator; and

a local fourth gate formed over the second dielectric layer, each of the local third and fourth gates configured to be capacitively coupled to the channel of the bilayer graphene layer;

wherein the local third and fourth gates form at least a second pair of gates to locally control at least a second portion of the bilayer graphene layer;

wherein the at least second pair of gates operates as gates of a second transistor; and

wherein the local third gate is controllable independent of the local fourth gate.

16. The integrated circuit of claim 15 , wherein at least one of the local first, second, third and fourth gates comprises metal material.

17. The integrated circuit of claim 15 , wherein at least one of the local first, second, third and fourth gates having a channel length of approximately one (1) nm to approximately one (1) μm.

18. The integrated circuit of claim 15 , wherein at least one of the local first, second, third and fourth gates comprises poly-silicon.

19. The integrated circuit of claim 15 , wherein the first transistor having a threshold voltage that is determined by the local first and second gates.

20. The integrated circuit of claim 15 , wherein the at least second transistor having a threshold voltage that is determined by the local third and fourth gates.