Verify pulse delay to improve resistance window
View Patent ↗Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of programming/erasing the programmable impedance element can include: (i) receiving a program/erase command to be executed on the programmable impedance element; (ii) generating, in response to the program/erase command, a program/erase pulse for performing a program/erase operation on the programmable impedance element; (iii) generating a time delay from the program/erase pulse, where the time delay includes additional delay to allow for at least partial dissipation of one or more effects caused by the program/erase operation; and (iv) performing, after the time delay has elapsed, a verify operation to determine if the program/erase operation has successfully programmed/erased the programmable impedance element.
1. A method of programming a programmable impedance element, the method comprising:
a) receiving a program command to be executed on the programmable impedance element;
b) generating, in response to the program command, a program pulse for performing a program operation on the programmable impedance element;
c) generating a time delay from the program pulse, wherein the time delay comprises a duration sufficient to allow for at least partial dissipation of one or more effects caused by the program operation, wherein the generating the time delay comprises accessing a data value from a register, wherein the data value corresponds to a time delay set by characterization of the programmable impedance element; and
d) performing, after the time delay has elapsed, a verify operation to determine if the program operation has successfully programmed the programmable impedance element.
2. The method of claim 1 , wherein the program operation comprises a plurality of program pulses.
3. The method of claim 2 , further comprising repeating, for each of the plurality of program pulses, the generating the time delay and the performing the verify operation after the time delay has elapsed.
4. The method of claim 3 , wherein the plurality of program pulses occur prior to any verify operation.
5. The method of claim 1 , wherein the time delay comprises an inherent delay plus a programmable delay.
6. The method of claim 1 , wherein the performing the program operation comprises selecting an option variable for at least one of pulse widths, voltages, and currents.
7. The method of claim 1 , wherein the generating the time delay comprises:
a) determining a temperature; and
b) setting the time delay based on the determined temperature.
8. The method of claim 1 , wherein the generating the time delay comprises:
a) determining an endurance life cycle; and
b) setting the time delay based on the determined endurance life cycle.
9. A method of erasing a programmable impedance element, the method comprising:
a) receiving an erase command to be executed on the programmable impedance element;
b) generating, in response to the erase command, an erase pulse for performing an erase operation on the programmable impedance element;
c) generating a time delay from the erase pulse, wherein the time delay comprises a duration sufficient to allow for at least partial dissipation of one or more effects caused by the erase operation, wherein the generating the time delay comprises accessing a data value from a register, wherein the data value corresponds to a time delay set by characterization of the programmable impedance element; and
d) performing, after the time delay has elapsed, a verify operation to determine if the erase operation has successfully erased the programmable impedance element.
10. The method of claim 6 , wherein the erase operation comprises a plurality of erase pulses.
11. The method of claim 10 , further comprising repeating, for each of the plurality of erase pulses, the generating the time delay and the performing the verify operation after the time delay has elapsed.
12. The method of claim 11 , wherein the plurality of erase pulses occur prior to any verify operation.
13. The method of claim 9 , wherein the time delay comprises an inherent delay plus a programmable delay.
14. The method of claim 9 , wherein the performing the erase operation comprises selecting an option variable for at least one of pulse widths, voltages, and currents.
15. The method of claim 9 , wherein the generating the time delay comprises:
a) determining a temperature; and
b) setting the time delay based on the determined temperature.
16. The method of claim 6 , wherein the generating the time delay comprises:
a) determining an endurance life cycle; and
b) setting the time delay based on the determined endurance life cycle.
17. An apparatus, comprising:
a) a command decoder configured to receive a program/erase command to be executed on a programmable impedance element;
b) a program/erase operation controller configured to generate, in response to the program/erase command, a write pulse for performing a program/erase operation on the programmable impedance element;
c) a delay controller configured to generate a time delay from the write pulse, wherein the time delay comprises a duration sufficient to allow for at least partial dissipation of one or more effects on the programmable impedance element caused by the program/erase operation;
d) a register configured to store a data value that is accessed to generate the time delay, wherein the data value corresponds to a time delay set by characterization of the programmable impedance element; and
e) a verify operation controller configured to perform a verify operation to determine if the program/erase operation has successfully written the programmable impedance element, wherein the verify operation begins after the time delay has elapsed.
18. The apparatus of claim 17 , wherein the register is coupled to the verify operation controller and the delay controller, and wherein the delay controller is configured to enable or disable predetermined delay elements based on the data value.