Method to fabricate copper wiring structures and structures formed thereby
View Patent ↗Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.
1. A wiring structure comprising:
a dielectric layer overlying a substrate, wherein said dielectric layer includes an opening within said dielectric layer;
a diffusion barrier lining said opening;
a conformal ruthenium layer on said diffusion barrier; and
a void-free copper layer on said ruthenium layer, wherein said copper layer has an impurity element selected from the group consisting of Cl, S, and a combination thereof, wherein the concentration of each impurity element is less than 20 ppm, and wherein said void-free copper layer is formed by sputter deposition followed by a reflow anneal.
2. The wiring structure of claim 1 , wherein said opening exposes a topmost surface of said substrate.
3. The wiring structure of claim 1 , wherein said opening includes a line or a via.
4. The wiring structure of claim 1 , wherein said dielectric layer comprises a material selected from the group consisting of SiO 2 and SiCOH.
5. The wiring structure of claim 1 , wherein said dielectric layer has a thickness of between 10 nm and 1,000 nm.
6. The wiring structure of claim 1 , wherein the copper layer comprises another impurity element selected from the group consisting of C, O, and a combination thereof, wherein the concentration of each of said another impurity element is less than 40 ppm.
7. The wiring structure of claim 1 , wherein said conformal ruthenium layer has a thickness of from about 1 nanometer to about 10 nanometers.
8. The wiring structure of claim 7 , wherein the ruthenium layer has a thickness of from about 2 nanometers to about 5 nanometers.
9. The wiring structure of claim 1 , wherein said copper layer has a thickness of from about 50 nanometers to about 300 nanometers.
10. The wiring structure of claim 9 , wherein said copper layer has a thickness of from about 100 nanometers to about 200 nanometers.
11. The wiring structure of claim 1 , wherein said diffusion barrier is in direct and continuous contact with an entire exposed sidewall surface of said opening.
12. The wiring structure of claim 1 , wherein said conformal ruthenium layer is in direct and continuous contact with an entire exposed sidewall surface of said diffusion barrier.
13. The wiring structure of claim 1 , wherein said copper layer is in direct and continuous contact with an entire exposed sidewall surface of said ruthenium layer.
14. The wiring structure of claim 1 , wherein said diffusion barrier comprises:
a tantalum nitride layer lining said opening; and
a tantalum layer on said tantalum nitride layer.
15. The wiring structure of claim 14 , wherein said tantalum nitride layer has a thickness of from about 5 nanometers to about 15 nanometers.
16. The wiring structure of claim 15 , wherein said tantalum nitride layer has a thickness of from about 8 nanometers to about 12 nanometers.
17. The wiring structure of claim 14 , wherein said tantalum layer has a thickness of from about 5 nanometers to about 15 nanometers.
18. The wiring structure of claim 17 , wherein said tantalum layer has a thickness of from about 8 nanometers to about 12 nanometers.
19. The wiring structure of claim 14 , wherein said tantalum nitride layer is in direct physical contact with an entire exposed sidewall surface of said opening, and said tantalum layer is in direct physical contact with an entire exposed sidewall surface of said tantalum nitride layer.