Contact resistance reduction employing germanium overlayer pre-contact metalization
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
1. A transistor device, comprising:
a substrate having a channel region;
source and drain regions in the substrate and adjacent to the channel region;
a boron doped germanium layer on at least a portion of the source and drain regions, the boron doped germanium layer comprising a germanium concentration in excess of 90 atomic % and a boron concentration in excess of 1E20 cm −3 ; and
a metal-germanide contact on the boron doped germanium layer.
2. The device of claim 1 wherein the device is one of a planar or FinFET transistor.
3. The device of claim 1 wherein the device comprises a PMOS transistor.
4. The device of claim 1 further comprising at least one of:
a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region;
first and second metal-germanide contacts on the boron doped germanium layer, each over a corresponding one of the source and drain regions; and
an interlayer dielectric.
5. The device of claim 1 , further comprising at least one of:
a graded buffer between the substrate and the source and drain regions; and
a graded buffer between at least one of the source and drain regions and the boron doped germanium layer.
6. The device of claim 5 wherein the graded buffer between at least one of the source and drain regions and the boron doped germanium layer has a germanium concentration that is graded from a base level concentration compatible with the source and drain regions to a high concentration in excess of 95 atomic %.
7. The device of claim 6 wherein the high concentration reflects pure germanium.
8. The device of claim 5 wherein the graded buffer between at least one of the source and drain regions and the boron doped germanium layer has a boron concentration that is graded from a base level concentration compatible with the source and drain regions to a high concentration in excess of 1E20 cm −3 .
9. The device of claim 1 wherein the boron doped germanium layer has a graded concentration of at least one of germanium and boron.
10. The device of claim 9 wherein the boron doped germanium layer has a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 90 atomic %.
11. The device of claim 9 wherein the boron doped germanium layer has a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 1E20 cm −3 .
12. The device of claim 1 wherein the source and drain regions comprise silicon or silicon germanium, and the device further comprises a buffer between the source and drain regions and the boron doped germanium layer, the buffer having a germanium concentration that is graded from a base level concentration compatible with the source and drain regions to a high concentration in excess of 50 atomic %, and a boron concentration that is graded from a base level concentration compatible with the source and drain regions to a high concentration in excess of 1E20 cm −3 .
13. The device of claim 1 wherein the boron doped germanium layer comprises a germanium concentration in excess of 98 atomic %, and a boron concentration in excess of 2E20 cm −3 .
14. An electronic device comprising:
a printed circuit board having one or more integrated circuits, wherein at least one of the one or more integrated circuits comprises one or more transistor devices as defined in claim 1 .
15. A transistor device, comprising:
a substrate having a channel region;
a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode;
source and drain regions in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under the gate dielectric layer and/or a corresponding one of the spacers;
a boron doped germanium layer on at least a portion of the source and drain regions, the boron doped germanium layer comprising a germanium concentration in excess of 95 atomic % and a boron concentration in excess of 2E20 cm −3 ; and
first and second metal-germanide contacts on the boron doped germanium layer, each over a corresponding one of the source and drain regions;
wherein the device is one of a planar or FinFET transistor.
16. The device of claim 15 wherein the boron doped germanium layer has a graded concentration of at least one of germanium and boron.
17. The device of claim 16 wherein the boron doped germanium layer has a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 90 atomic %.
18. The device of claim 16 wherein the boron doped germanium layer has a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 1E20 cm −3 .
19. A method for forming a transistor device, comprising:
providing a substrate having a channel region;
providing a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region;
providing source and drain regions in the substrate and adjacent to the channel region;
providing a boron doped germanium layer on at least a portion of the source and drain regions, the boron doped germanium layer comprising a germanium concentration in excess of 90 atomic % and a boron concentration in excess of 1E20 cm −3 ;
providing a first metal-germanide contact on the boron doped germanium layer and over the source region; and
providing a second metal-germanide contact on the boron doped germanium layer and over the drain region.
20. The method of claim 19 wherein the boron doped germanium layer has a graded concentration of at least one of germanium and boron.