Semiconductor packages with pillar and bump structures

1. A semiconductor structure comprising:

a semiconductor die having a surface of the semiconductor die;

a first contact pad located on the surface;

a conductive pillar in direct contact with the first contact pad, the conductive pillar having a width that is less than a width of the first contact pad;

an encapsulation layer located over the surface and around side surfaces of the conductive pillar, a surface of the encapsulation material being coplanar with a surface of the conductive pillar;

a redistribution layer covering the encapsulation layer such that the encapsulation material is between the redistribution layer and the surface of the semiconductor die, the redistribution layer including a trace and a redistributed contact pad, the redistributed contact pad being laterally offset from the first contact pad and in electrical communication with the first contact pad by the conductive pillar; and

a conductive bump on the redistribution contact pad that is located above the encapsulation layer.

2. The semiconductor structure of claim 1 wherein the conductive pillar is located on the first contact pad.

3. The semiconductor structure of claim 1 wherein the redistribution layer is located over the conductive pillar.

4. The semiconductor structure of claim 1 wherein the conductive pillar has a first surface and the encapsulation layer has a second surface, wherein the first surface is flush with the second surface.

5. The semiconductor structure of claim 1 wherein the encapsulation layer is a molding compound.

6. The semiconductor structure of claim 5 wherein the molding compound is a resin.

7. The semiconductor structure of claim 1 wherein the semiconductor die has a perimeter and includes a recess at the perimeter of the die.

8. A method comprising:

forming conductive pillars directly on contact pads of a surface of a semiconductor die, the conductive pillars having widths that are less than widths of the contact pads;

forming an encapsulation layer over the surface of the semiconductor die and at least along side surfaces of the conductive pillars;

planarizing the encapsulation layer to expose surfaces of the conductive pillars such that the exposed surfaces of the conductive pillars are coplanar with a surface of the encapsulation material;

forming a redistribution layer over the encapsulation layer such that the encapsulation material is between the redistribution layer and the surface of the semiconductor die, the redistribution layers including traces and redistributed contact pads that are in electrical communication with the contact pads by the conductive pillars, respectively; and

forming conductive bumps on the redistribution contact pads, the conductive bumps being above the encapsulation layer.

9. The method of claim 8 further comprising forming a recess at a perimeter of the semiconductor die at the surface, wherein forming the encapsulation layer includes filling the recess with the encapsulation layer.

10. The method of claim 8 further comprising forming recesses in the wafer between a plurality of semiconductor dice, wherein forming the encapsulation layer comprises filling the recesses with the encapsulation layer.

11. The method of claim 8 wherein forming the encapsulation layer comprises using a mold to inject a molding compound.

12. A semiconductor package comprising:

a semiconductor die;

a first contact pad located on a surface of the semiconductor die;

a conductive pillar located on and in direct contact with the first contact pad, the conductive pillar having a width that is less than a width of the first contact pad;

an encapsulation layer surrounding side surfaces of the conductive pillar and covering a portion of the first contact pad, a surface of the encapsulation material being coplanar with a surface of the conductive pillar;

a redistribution layer including a trace and a redistributed contact pad covering the encapsulation layer such that the encapsulation layer is between the surface of the semiconductor die and the redistribution layer, the redistributed contact pad in electrical communication with the first contact pad by the conductive pillar; and

a conductive bump on the redistribution contact pad and located above the encapsulation layer.

13. The semiconductor package of claim 12 wherein the conductive pillar has a smaller cross sectional dimension than an exposed surface of the first contact pad.

14. The semiconductor package of claim 12 wherein the trace of the redistribution layer covers the pillar.