IP Library Patent Application 14678223
Patent Application
App. No. 14/678,223

STACKED INTERCONNECT HEAT SINK

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Quick Facts
Patent No.
US None
App. No.
14/678,223
Abstract

A method is provided. The method includes providing an integrated circuit having a substrate. The method also includes locating a via within the substrate. The method further includes connecting the via to a corresponding heat spreader via. The corresponding heat spreader via may pass through a thermally conductive core of a heat spreader.

Claims (29)

1 . A method of forming an electronic device, comprising:

providing an integrated circuit having a substrate;

locating an active via within said substrate; and

connecting said active via to a corresponding heat spreader via that passes through a thermally conductive core of a heat spreader.

2 . The method as recited in claim 1 , wherein said thermally conductive core is an electrically conductive layer.

3 . The method as recited in claim 2 , further comprising locating a dielectric layer between said heat spreader via and said thermally conductive core, and forming a solder pad on a surface of said thermally conductive core.

4 . The method as recited in claim 1 , wherein said thermally conductive core is an electrically insulating layer.

5 . The method as recited in claim 4 , further comprising forming a metallurgical connection between a heat spreader plug located within said electrically insulating layer with a substrate plug located within said substrate.

6 . The method as recited in claim 1 , further comprising locating a substrate plug within said substrate and connecting said substrate plug to said heat spreader.

7 . A method of forming an electronic device, comprising:

providing an integrated circuit having a substrate;

locating a via within said substrate; and

connecting said via to a corresponding heat spreader via that passes through a thermally conductive core of a heat spreader.

8 . The method as recited in claim 7 , wherein said thermally conductive core is an electrically conductive layer.

9 . The method as recited in claim 8 , further comprising locating a dielectric layer between said heat spreader via and said thermally conductive core, and forming a solder pad on a surface of said thermally conductive core.

10 . The method as recited in claim 7 , wherein said thermally conductive core is an electrically insulating layer.

11 . The method as recited in claim 10 , further comprising forming a metallurgical connection between a heat spreader plug located within said electrically insulating layer with a substrate plug located within said substrate.

12 . The method as recited in claim 7 , further comprising locating a substrate plug within said substrate and connecting said substrate plug to said heat spreader.

13 . A method, comprising:

providing an integrated circuit having a substrate;

locating a via within said substrate; and

connecting said via to a corresponding heat spreader via.

14 . The method as recited in claim 13 , wherein said corresponding heat spreader via passes through a thermally conductive core of a heat spreader.

15 . The method as recited in claim 14 , wherein said thermally conductive core is an electrically conductive layer.

16 . The method as recited in claim 15 , further comprising locating a dielectric layer between said heat spreader via and said thermally conductive core, and forming a solder pad on a surface of said thermally conductive core.

17 . The method as recited in claim 14 , wherein said thermally conductive core is an electrically insulating layer.

18 . The method as recited in claim 17 , further comprising forming a metallurgical connection between a heat spreader plug located within said electrically insulating layer with a substrate plug located within said substrate.

19 . The method as recited in claim 14 , further comprising locating a substrate plug within said substrate and connecting said substrate plug to said heat spreader.

20 . The method as recited in claim 13 , wherein said via is an active via.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2016
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038062/0967 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: BACHMAN, MARK A.; OSENBACH, JOHN W.; MERCHANT, SAILESH M.
To: LSI CORPORATION
Reel/Frame 035329/0027 →