FinFET conformal junction and abrupt junction with reduced damage method and device

1. A method comprising:

forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET;

forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode;

implanting a first dopant into the fin of the second polarity FET;

etching a cavity in the fin of the second polarity FET on each side of the gate electrode;

removing the first mask;

performing rapid thermal anneal (RTA);

epitaxially growing source/drain region of the second polarity FET in each cavity;

forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and

implanting a second dopant in the source/drain regions of the second polarity FET.

2. The method according to claim 1 , comprising implanting the first dopant at a dose of 1e14 cm −3 to 1e16 cm −3 .

3. The method according to claim 2 , comprising implanting the first dopant at an energy of 3 kiloelectron Volts (keV) to 10 keV.

4. The method according to claim 2 , comprising implanting the first dopant with zero tilt with respect to the sidewall of the fin.

5. The method according to claim 1 , comprising reducing a height of the spacers prior to etching the cavities.

6. The method according to claim 1 , comprising removing the first mask by ashing and chemical cleaning.

7. The method according to claim 1 , further comprising precleaning prior to epitaxially growing the source/drain regions of the second polarity FET.

8. The method according to claim 1 , comprising implanting the second dopant at a dose of 1e14 cm −3 to 1e16 cm −3 .

9. The method according to claim 8 , comprising implanting the second dopant at an energy of 0.5 keV to 5 keV.

10. The method according to claim 8 , comprising implanting the second dopant with zero degrees of rotation and with a maximum tilt.

11. The method according to claim 1 , wherein the first and second dopants comprise arsenic.

12. A method comprising:

forming a PFET fin and an NFET fin on a substrate;

forming shallow trench isolation regions between the PFET fin and the NFET fin;

forming a gate electrode over and perpendicular to the PFET fin and the NFET fin;

forming PFET source/drain regions on the PFET fin at opposite sides of the gate electrode;

forming a first mask over the PFET fin and PFET source/drain regions;

forming spacers on sidewalls of the NFET fin on each side of the gate electrode;

implanting arsenic into the NFET fin at a dose of 1e14 cm −3 to 1e16 cm −3 and with zero tilt with respect to the fin sidewall;

reducing a height of the spacers;

etching a cavity in the NFET fin on each side of the gate electrode;

removing the first mask;

performing rapid thermal anneal (RTA);

epitaxially growing an NFET source/drain region in each cavity;

forming a second mask over the PFET fin and PFET source/drain regions;

implanting arsenic in the NFET source/drain regions at a dose of 1e14 cm −3 to 1e16 cm −3 and with zero degrees of rotation and a maximum tilt; and

implanting boron or boron fluoride (BF 2 ) into the PFET source/drain regions.

13. The method according to claim 12 , comprising implanting the arsenic into the NFET fin at an energy of 3 kiloelectron Volts (keV) to 10 keV and implanting the arsenic into the NFET source/drain regions at an energy of 0.5 keV to 5 keV.

14. The method according to claim 12 , comprising removing the first mask by ashing and chemical cleaning.

15. The method according to claim 12 , further comprising precleaning prior to epitaxially growing the NFET source/drain regions.