Mismatch-compensated sense amplifier for highly scaled technology
Circuits and methods are provided for compensating an offset voltage measured between a first transistor and a second transistor of a sense amplifier circuit that is configured to sense a bit line signal during a sensing phase. The first transistor and the second transistor are cross-coupled. The first transistor is coupled to a first capacitor and the second transistor is coupled to a second capacitor. The first capacitor is further coupled to the second capacitor, and the first and second capacitors are coupled to a third transistor. The first capacitor applies a first bias voltage to the first transistor during a pre-sensing phase prior to the sensing phase, and the second capacitor applies a second bias voltage to the second transistor during the pre-sensing phase.
1. An integrated circuit comprising:
a memory having a plurality of memory cells; and
a sense amplifier coupled to the memory, the sense amplifier configured to sense a bit line signal selected from the plurality of memory cells during a sensing phase, the sense amplifier including:
a first transistor having a control electrode coupled with a first current electrode of a second transistor, the second transistor having a control electrode coupled with a first current electrode of the first transistor,
a first capacitor having a first electrode coupled to a second current electrode of the first transistor, wherein
the first capacitor is configured to apply a first bias voltage to the second current electrode of the first transistor during a pre-sensing phase prior to the sensing phase,
a second capacitor having a first electrode coupled to a second current electrode of the second transistor, the second capacitor having a second electrode coupled to a second electrode of the first capacitor, wherein
the second capacitor is configured to apply a second bias voltage to the second electrode of the second transistor during the pre-sensing phase, and
the first and second bias voltages are configured to compensate an offset voltage measured between the first and second transistors,
a third transistor coupled between the second electrodes of the first and second capacitors and a first power supply voltage,
a fourth transistor coupled between the second electrodes of the first and second capacitors and the first power supply voltage, and
a third capacitor coupled between the second electrodes of the first and second capacitors and the third transistor.
2. The integrated circuit of claim 1 , wherein
the first and second bias voltages are respectively applied to the first and second transistors to equalize a first current passed by the first transistor and a second current passed by the second transistor during the pre-sensing phase.
3. The integrated circuit of claim 1 , further comprising:
a precharge transistor coupled between the second electrodes of the first and second capacitors and a second power supply voltage, the precharge transistor configured to precharge the second electrodes of the first and second capacitors to the second power supply voltage during a pre-charging phase prior to the pre-sensing phase.
4. The integrated circuit of claim 3 , wherein
the first transistor has a first threshold voltage,
the second transistor has a second threshold voltage, and
the third transistor is configured to
adjust a voltage stored on the first electrode of the first capacitor to the first bias voltage subsequent to the pre-charging phase, wherein the first bias voltage is substantially the second power supply voltage reduced by the first threshold voltage, and
adjust a voltage stored on the first electrode of the second capacitor to the second bias voltage subsequent to the pre-charging phase, wherein the second bias voltage is substantially the second power supply voltage reduced by the second threshold voltage.
5. The integrated circuit of claim 1 , further comprising:
a fifth transistor having a control electrode coupled to the control electrode of the first transistor, having a first current electrode coupled to the first current electrode of the first transistor, and having a second current electrode coupled to a second power supply voltage; and
a sixth transistor having a control electrode coupled to the control electrode of the second transistor, having a first current electrode coupled to the first current electrode of the second transistor, and having a second current electrode coupled to the second power supply voltage.
6. The integrated circuit of claim 5 , wherein
the first transistor, the second transistor, and the third transistor are of a first type of transistor, and
the fourth transistor, the fifth transistor, and the sixth transistor are of a second type of transistor.
7. The integrated circuit of claim 1 , further comprising:
a first isolation transistor coupled between a first bit line and a first input of the sense amplifier, wherein the first input comprises the second current electrode of the first transistor;
a second isolation transistor coupled between a second bit line and a second input of the sense amplifier, wherein the second input comprises the second current electrode of the second transistor; and
wherein the first and second isolation transistors are configured to electrically isolate the sense amplifier from the first and second bitlines prior to a portion of a sensing phase.
8. A sense amplifier circuit comprising:
a first transistor of a first type having a first current electrode coupled to a first node, a second current electrode coupled to a first electrode of a first capacitor, and a control electrode coupled to a second node;
a second transistor of the first type having a first current electrode coupled to the second node, a second current electrode coupled to a first electrode of a second capacitor, and a control electrode coupled to the first node, wherein
the second capacitor has a second electrode coupled to a second electrode of the first capacitor;
a third transistor of the first type having a first current electrode and a second current electrode coupled to a first power supply voltage, and a control electrode coupled to a first sense enable signal, and
a third capacitor having a first electrode coupled to the second electrode of the first capacitor and the second electrode of the second capacitor, and having a second electrode coupled to a drain electrode of the third transistor.
9. The sense amplifier circuit of claim 8 , further comprising:
a precharge transistor of a second type having a first current electrode coupled to a second power supply voltage, a second current electrode coupled to the second electrodes of the first and second capacitors, and a control electrode coupled to a precharge control signal.
10. The sense amplifier circuit of claim 8 , further comprising:
a fourth transistor having a drain electrode coupled to the second electrode of the first capacitor and the second electrode of the second capacitor, a source electrode coupled to the first power supply voltage, and a control electrode coupled to a second sense enable signal.
11. The sense amplifier circuit of claim 8 , further comprising:
a fifth transistor of a second type having a source electrode coupled to a second power supply voltage, having a drain electrode coupled to the first node, and having a control electrode coupled to the second node; and
a sixth transistor having a source electrode coupled to the second power supply voltage, having a drain electrode coupled to the second node, and having a control electrode coupled to the first node.
12. The sense amplifier circuit of claim 8 , further comprising:
a first isolation transistor having a first current electrode coupled to a first bit line, having a second current electrode coupled to the first node, and having a control electrode coupled to an isolation control signal; and
a second isolation transistor having a first current electrode coupled to an a second bitline, having a second current electrode coupled to the second node, and having a control electrode coupled to the isolation control signal.
13. A method comprising:
compensating an offset voltage measured between a first transistor and a second transistor of a sense amplifier circuit, wherein
the sense amplifier circuit is configured to sense a bit line signal during a sensing phase,
the compensating is performed during a pre-sensing phase prior to the sensing phase,
the first transistor and the second transistor are cross-coupled,
the first transistor is further coupled to a first capacitor,
the second transistor is further coupled to a second capacitor,
the first capacitor is further coupled to the second capacitor,
the first and second capacitors are further coupled to a third transistor that is coupled to a first power supply voltage,
the first and second capacitors are further coupled to a third capacitor that is coupled to a drain electrode of the third transistor, and
the compensating comprises:
applying a first bias voltage to the first transistor during the pre-sensing phase, wherein the first bias voltage is stored on the first capacitor wherein the first bias voltage is substantially the second power supply reduced by the threshold voltage of the first transistor,
applying a second bias voltage to the second transistor during the pre-sensing phase, wherein the second bias voltage is stored on the second capacitor wherein the second bias voltage is substantially the second power supply reduced by the threshold voltage of the second transistor.
14. The method of claim 13 , further comprising:
pre-charging a common node of the first capacitor and the second capacitor to a second power supply voltage, wherein the pre-charging is performed during a pre-charging phase prior to the pre-sensing phase.
15. The method of claim 13 , further comprising:
developing the bit line signal and transferring the signal to the sense amplifier in response to a word line selection, wherein
the developing and transferring is performed subsequent to the compensating.
16. The method of claim 15 further comprising isolating the amplifier from the bitline.
17. The method of claim 16 , further comprising:
sensing the bit line signal during the sensing phase; and
amplifying the bit line signal.