Embedded die ball grid array package
View Patent ↗A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.
1. A semiconductor package, comprising:
a semiconductor die having opposing first and second main surfaces, wherein the second main surface includes a plurality of pads for communication with internal circuitry of the semiconductor die;
at least one stud bump formed on one of the pads on the second main surface of the semiconductor die;
at least one die conductive member electrically coupled to the at least one stud bump;
at least one grid array conductive member electrically coupled to the at least one die conductive member;
an encapsulation material encapsulating the semiconductor die, the at least one stud bump, and the at least one die conductive member, wherein at least a portion of the at least one grid array conductive member is exposed through the encapsulation material; and
a solder ball electrically coupled to the at least one grid array conductive member.
2. The semiconductor package of claim 1 , further comprising a solder mask formed on the encapsulation material.
3. The semiconductor package of claim 2 , wherein the solder mask includes at least one opening through which the solder ball is electrically coupled to the at least one grid array conductive member.
4. The semiconductor package of claim 1 , further comprising at least one intermediate conductive member formed on the encapsulation material on a surface opposite to the solder ball, the at least one intermediate conductive member electrically coupling the at least one die conductive member to the at least one grid array conductive member.
5. The semiconductor package of claim 1 , wherein the encapsulation material is an epoxy.
6. The semiconductor package of claim 1 , further comprising a frame, wherein the first surface of the semiconductor die is attached to the frame.
7. The semiconductor package of claim 6 , wherein a portion of the encapsulation material separates the first main surface of the semiconductor die from the frame.