IP Library Granted Patent US 9,281,367
Granted Patent B2
US 9,281,367 · App. 14/697,615 · Granted Mar 8, 2016

Semiconductor structure having contact plug and method of making the same

Inventors: Ching-Wen Hung (Tainan, TW); Chih-Sen Huang (Tainan, TW); Po-Chao Tsao (New Taipei, TW); Chieh-Te Chen (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/41758H01L21/283H01L21/32115H01L21/76816H01L21/76877H01L21/76897H01L23/485H01L23/528H01L23/53209H01L29/45H01L29/665H01L29/66545H01L29/66575H01L29/78H01L29/7845H01L29/7848H01L23/53223H01L23/53238H01L23/53266H01L23/53295H01L29/165H01L29/41725H01L29/41783H01L29/7843H01L2924/0002
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Quick Facts
Patent No.
US 9,281,367
App. No.
14/697,615
Granted
Mar 8, 2016
Kind
B2
Abstract

The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.

Claims (17)

1. A semiconductor structure having at least a contact plug, comprising:

a substrate;

a transistor disposed on the substrate, wherein the transistor comprises a gate and a source/drain region;

a first inter-layer dielectric (ILD) layer disposed on the transistor, wherein a bottom surface of the first ILD layer is level with a top surface of the gate;

a first contact plug disposed in the first ILD layer to electrically connect the source/drain region, wherein a top surface of the first contact plug is higher than a top surface of the gate and a top surface of the first contact plug is level with a top surface of the first ILD layer;

a second ILD layer disposed on the first ILD layer;

a second contact plug disposed in the second ILD layer to electrically connect the first contact plug; and

a third contact plug disposed in the first ILD layer and the second ILD layer to electrically connect the gate.

2. The semiconductor structure having at least a contact plug as in claim 1 , wherein the first ILD layer disposed on the gate has a predetermined thickness.

3. The semiconductor structure having at least a contact plug as in claim 2 , wherein the predetermined thickness is greater than 100 angstroms.

4. The semiconductor structure having at least a contact plug as in claim 1 , wherein the source/drain region comprises an epitaxial layer protruding above the substrate.

5. The semiconductor structure having at least a contact plug as in claim 1 , wherein the transistor further comprises a silicide layer disposed between the first contact plug and the source/drain region.

6. The semiconductor structure having at least a contact plug as in claim 1 , wherein both the second contact plug and the third contact plug comprise a second metal layer.

7. The semiconductor structure having at least a contact plug as in claim 6 , wherein the second metal layer comprises copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), niobium (Nb) or molybdenum (Mo).

8. The semiconductor structure having at least a contact plug as in claim 6 , wherein the first contact plug comprises a first metal layer, and the material of the first metal layer is different from that of the second metal layer.

9. The semiconductor structure having at least a contact plug as in claim 1 , wherein the first contact plug comprises a first metal layer, the second contact plug comprises a second metal layer and the third metal layer comprises a third metal layer, wherein the materials of the first metal layer, the second metal layer and the third metal layer are different from each other.

10. The semiconductor structure having at least a contact plug as in claim 1 , further comprising an etch stop layer disposed between the first ILD layer and the second ILD layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2026
From: STELLAR SEMICONDUCTOR JAPAN GK
To: STELLAR SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 075432/0270 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2025
From: UNITED MICROELECTRONICS CORP.
To: STELLAR SEMICONDUCTOR JAPAN GK
Reel/Frame 071913/0125 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2015
From: HUNG, CHING-WEN; HUANG, CHIH-SEN; TSAO, PO-CHAO; CHEN, CHIEH-TE
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 035506/0440 →
Continuity (2)
Continuation 13705175 · Dec 5, 2012
Related Publication 20150228734A1 · Aug 13, 2015