Semiconductor substrate, semiconductor package structure and method of making the same

1. A method of making a semiconductor substrate, comprising:

providing a substrate, the substrate comprising:

a first patterned metal layer;

a second patterned metal layer spaced from the first patterned metal layer;

a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer and covering the second patterned metal layer, wherein the dielectric layer defines first openings exposing the second patterned metal layer, and the dielectric layer further defines a via opening extending from the first patterned metal layer to the second patterned metal layer; and

a conductive material disposed in the via opening and electrically connecting the first patterned metal layer to the second patterned metal layer; and

providing a carrier layer on the dielectric layer, wherein the carrier layer defines second openings exposing the second patterned metal layer.

2. The method of making a semiconductor substrate according to claim 1 , wherein the carrier layer further comprises a third patterned metal layer and a supporting layer, the third patterned metal layer abutting the dielectric layer, and the supporting layer abutting the third patterned metal layer.

3. The method of making a semiconductor substrate according to claim 1 , wherein the dielectric layer comprises a first dielectric sub-layer and a second dielectric sub-layer, the first dielectric sub-layer being disposed between the first patterned metal layer and the second patterned metal layer, the second dielectric sub-layer abutting the first dielectric sub-layer and covering the second patterned metal layer, and the second dielectric sub-layer defining the first openings exposing the second patterned metal layer.

4. The method of making a semiconductor substrate according to claim 1 , wherein the dielectric layer is a photosensitive material.

5. The method of making a semiconductor substrate according to claim 1 , wherein providing a substrate comprises:

forming the first patterned metal layer on a metal foil;

forming a first dielectric sub-layer on the first patterned metal layer and the metal foil;

forming the second patterned metal layer on the first dielectric sub-layer, and electrically connecting the second patterned metal layer to the first patterned metal layer; and

forming a second dielectric sub-layer on the second patterned metal layer and the first dielectric sub-layer, wherein the first dielectric sub-layer and the second dielectric sub-layer fuse to form the dielectric layer.

6. The method of making a semiconductor substrate according to claim 5 , wherein providing a substrate further comprises, subsequent to forming the first dielectric sub-layer, forming via openings in the first dielectric sub-layer to expose part portions of the first patterned metal layer.

7. The method of making a semiconductor substrate according to claim 1 , wherein a diameter of each of the second openings is greater than or equal a diameter of a respective one of the first openings.

8. A method of making a semiconductor package structure, comprising:

providing a semiconductor substrate, the semiconductor substrate comprising:

a first patterned metal layer;

a second patterned metal layer spaced from the first patterned metal layer;

a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer and covering the second patterned metal layer, wherein the dielectric layer defines first openings exposing the second patterned metal layer, and the dielectric layer further defines a via opening extending from the first patterned metal layer to the second patterned metal layer;

a conductive material disposed in the via opening and electrically connecting the first patterned metal layer to the second patterned metal layer; and

a carrier layer abutting the dielectric layer, the carrier layer defining second openings exposing the second patterned metal layer;

electrically connecting a die to the first patterned metal layer; and

removing the carrier layer.

9. The method of making a semiconductor package structure according to claim 8 , wherein the carrier layer comprises a third patterned metal layer and a supporting layer, the third patterned metal layer abuts the dielectric layer, and the supporting layer abuts the third patterned metal layer.

10. The method of making a semiconductor package structure according to claim 8 , wherein the dielectric layer comprises a first dielectric sub-layer and a second dielectric sub-layer, the first dielectric sub-layer being disposed between the first patterned metal layer and the second patterned metal layer, the second dielectric sub-layer abuts the first dielectric sub-layer and covers the second patterned metal layer, and the second dielectric sub-layer defines the first openings exposing the second patterned metal layer.

11. The method of making a semiconductor package structure according to claim 8 , wherein before removing the carrier layer, the method further comprises: forming solder balls in the first openings and the second openings.

12. The method of making a semiconductor package structure according to claim 8 , wherein the first patterned metal layer is embedded in the dielectric layer and exposed from the dielectric layer.

13. The method of making a semiconductor package structure according to claim 8 , wherein the dielectric layer is a photosensitive material.

14. The method of making a semiconductor package structure according to claim 8 , wherein before removing the carrier layer, the method further comprises: forming a molding compound to cover the die.

15. The method of making a semiconductor package structure according to claim 8 , wherein a diameter of each of the second openings is greater than or equal to a diameter of a corresponding one of the first openings.

16. A method, comprising:

providing a substrate;

applying a carrier layer to the substrate, wherein the carrier layer defines openings exposing portions of the substrate;

disposing solder on the substrate within ones of the openings in the carrier layer; and

removing the carrier layer;

wherein the substrate comprises a dielectric layer, a first patterned metal layer embedded in a first surface of the dielectric layer, a second patterned metal layer embedded in the dielectric layer and partially exposed from a second surface of the dielectric layer, and a conductive material disposed in an opening through the dielectric layer, the conductive material electrically connecting the first patterned metal layer and the second patterned metal layer; and

wherein the exposed portions of the substrate include portions of the second patterned metal layer partially exposed from the dielectric layer, and the solder is disposed on the second patterned metal layer.

17. The method according to claim 16 , wherein the second patterned metal layer is recessed from the second surface of the dielectric layer.

18. The method according to claim 16 , wherein the dielectric layer comprises a plurality of dielectric layers, the first patterned metal layer is disposed in a first of the dielectric layers, and the second patterned metal layer is disposed in a second of the dielectric layers.

19. The method according to claim 16 , wherein providing the substrate comprises applying a first amount of a dielectric material over the first patterned metal layer, disposing the second metal layer on the dielectric material and through openings defined by the dielectric material, applying a second amount of the dielectric material over the second metal layer, and curing the dielectric material to form the dielectric layer.

20. The method according to claim 16 , wherein providing the substrate comprises providing a loading plate with the substrate disposed on a side of the loading plate, further comprising separating the substrate from the loading plate, attaching a die to the substrate at the first surface of the substrate, and encapsulating the die and the first surface of the substrate.