Integrated circuit with on chip planar diode and CMOS devices

1. A planar diode, comprising:

a substrate;

a diode region including a portion of the substrate, the diode region being electrically isolated from other substrate regions;

a first doped layer in the diode region above the substrate;

a second doped layer in the diode region above the first doped layer and above a middle undoped layer;

the middle undoped layer in the diode region above at least part of the first doped layer; and

an external undoped layer outside of the diode region, wherein the external undoped layer comprises a portion of at least one CMOS device in at least one of the other substrate regions, the first doped layer, the second doped layer, the middle undoped layer, and the external undoped layer each being epitaxial layers having a single respective crystal oriented by an orientation of the substrate, the middle undoped layer and the external undoped layer having been formed simultaneously.

2. The planar diode of claim 1 , wherein the first doped layer, the middle undoped layer and the second doped layer are configured together as a vertical PIN diode.

3. The planar diode of claim 1 , wherein the at least one CMOS device is one of an nFET or a pFET, the CMOS device having a doped source-drain epitaxial layer of the same material as the first doped layer.

4. The planar diode of claim 1 , wherein a width of the diode region is at least 10 times greater than a pitch of the at least one CMOS device.

5. The planar diode of claim 1 , wherein the substrate is a silicon on insulator wafer having a silicon layer above an insulator layer, the silicon layer being at least 40 nm thick.

6. The planar diode of claim 1 , wherein the first doped layer includes in-situ boron doped silicon germanium.

7. The planar diode of claim 1 , wherein the second doped layer includes at least one of in-situ phosphorus doped silicon and a combination of silicon and carbon.

8. The planar diode of claim 1 , wherein the first doped layer and the second doped layer are configured together as a vertical PN diode.

9. An electrical circuit, comprising:

a substrate;

a diode region including a portion of the substrate, the diode region being electrically isolated from other substrate regions;

a first doped layer above the substrate in the diode region;

a second doped layer above the first doped layer in the diode region and above a middle undoped layer;

the middle undoped layer in the diode region above at least part of the first doped layer;

an external undoped layer outside of the diode region, wherein the external undoped layer comprises a portion of at least one CMOS device in at least one of the other substrate regions, the first doped layer, the second doped layer, the middle undoped layer, and the external undoped layer each being epitaxial layers having a single respective crystal oriented by an orientation of the substrate, the middle undoped layer and the external undoped layer having been formed simultaneously, the first doped layer and the second doped layer are configured together as a diode;

a pFET above an n doped region in the substrate; and

an nFET above a p doped region in the substrate.

10. The electrical circuit of claim 9 , wherein the pFET includes a p doped source-drain epitaxial layer and the nFET includes an n doped source-drain epitaxial layer, the p doped source-drain epitaxial layer being the same material as one of the first doped layer and the second doped layer and the n doped source-drain epitaxial layer being the same material as an other of the first doped layer and the second doped layer.

11. The electrical circuit of claim 10 , wherein a thickness of at least one of the p doped source-drain epitaxial layer and the n doped source-drain epitaxial layer is less than a thickness of the first doped layer.

12. The electrical circuit of claim 9 , wherein a width of the diode region is at least 10 times greater than a pitch of at least one of the other substrate regions.