Chip package and method for forming the same
A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.
1. A chip package, comprising:
a first substrate comprising a sensing device, wherein the first substrate has a first opening, a first surface and a second surface opposite to the first surface;
a second substrate attached onto the first substrate, wherein the second substrate comprises an integrated circuit device;
a first conducting structure electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate;
an insulating layer covering the first substrate, the second substrate and the redistribution layer, wherein the insulating layer has a hole therein; and
a second conducting structure disposed under a bottom of the hole, and the second conducting structure is on the redistribution layer and in direct contact with the redistribution layer, wherein the redistribution layer conformally extends to sidewalls and a bottom of the first opening, and the first conducting structure and the second conducting structure are on the second surface and on opposite sides of the first opening.
2. The chip package as claimed in claim 1 , wherein a size of the first substrate is greater than that of the second substrate.
3. The chip package as claimed in claim 1 , wherein the sensing device is adjacent to the first surface, and the second substrate is attached to the second surface, and wherein the first substrate further comprises:
a conducting pad adjacent to the first surface, wherein the first opening extends from the second surface toward the first surface and exposes the conducting pad.
4. The chip package as claimed in claim 3 , wherein the redistribution layer is disposed on the second surface of the first substrate and is electrically connected to the exposed conducting pad through the first opening.
5. The chip package as claimed in claim 4 , wherein a material of the second conducting structure is the same as that of the first conducting structure.
6. The chip package as claimed in claim 1 , further comprising:
a metal layer disposed on the insulating layer and electrically connected to the second conducting structure through the hole; and
a third conducting structure electrically connected to the metal layer on the insulating layer.
7. The chip package as claimed in claim 6 , wherein a material of the third conducting structure is different from that of the second conducting structure.
8. The chip package as claimed in claim 6 , wherein the second conducting structure and the third conducting structure are bonding balls.
9. The chip package as claimed in claim 8 , wherein a size of the third conducting structure is greater than that of the second conducting structure.
10. The chip package as claimed in claim 1 , wherein the integrated circuit device comprises a signal processor.
11. The chip package as claimed in claim 1 , wherein the first conducting structure is disposed on the second substrate and extends onto the redistribution layer, and wherein the second conducting structure is disposed on the first substrate.
12. The chip package as claimed in claim 1 , wherein the first conducting structure is disposed on the second substrate and extends onto the redistribution layer, and wherein a fourth conducting structure is disposed on the second substrate.
13. The chip package as claimed in claim 1 , wherein the first conducting structure is disposed between the first substrate and the second substrate, and wherein the second conducting structure is disposed on the first substrate.
14. The chip package as claimed in claim 1 , wherein the sensing device is adjacent to the first surface, and the second substrate is attached to the second surface, and wherein the first substrate further comprises a conducting pad adjacent to the first surface.
15. The chip package as claimed in claim 14 , wherein the redistribution layer is disposed on the second surface of the first substrate and is electrically connected to the conducting pad.
16. The chip package as claimed in claim 1 , wherein a material of the second conducting structure is different from that of the first conducting structure.
17. The chip package as claimed in claim 16 , wherein a size of the second conducting structure is greater than that of the first conducting structure.
18. A method for forming a chip package, comprising:
providing a first substrate, wherein the first substrate comprises a sensing device and has a first surface and a second surface opposite to the first surface;
attaching a second substrate onto the first substrate, wherein the second substrate comprises an integrated circuit device;
forming a first opening in the first substrate;
forming a first conducting structure electrically connected to the sensing device and the integrated circuit device through a redistribution layer located on the first substrate, wherein the redistribution layer conformally extends to sidewalls and a bottom of the first opening; and
forming a second conducting structure and an insulating layer, wherein the insulating layer covers the first substrate, the second substrate and the redistribution layer, and the insulating layer has a hole therein, and wherein the second conducting structure is located under a bottom of the hole, and the second conducting structure is on the redistribution layer and in direct contact with the redistribution layer, and the first conducting structure and the second conducting structure are on the second surface and on opposite sides of the first opening.
19. The method as claimed in claim 18 , wherein a size of the first substrate is greater than that of the second substrate.
20. The method as claimed in claim 18 , wherein the sensing device is adjacent to the first surface, and the second substrate is attached to the second surface, and wherein the first substrate further comprises a conducting pad adjacent to the first surface, and wherein the first opening extends from the second surface toward the first surface and exposes the conducting pad, and wherein the redistribution layer is located on the second surface of the first substrate and is electrically connected to the exposed conducting pad through the first opening.
21. The method as claimed in claim 20 , wherein a material of the second conducting structure is the same as that of the first conducting structure.
22. The method as claimed in claim 18 , further comprising:
forming a metal layer on the insulating layer, wherein the metal layer is electrically connected to the second conducting structure through the hole; and
forming a third conducting structure on the metal layer on the insulating layer.
23. The method as claimed in claim 22 , wherein a material of the third conducting structure is different from that of the second conducting structure.
24. The method as claimed in claim 22 , wherein the second conducting structure and the third conducting structure are bonding balls.
25. The method as claimed in claim 24 , wherein a size of the third conducting structure is greater than that of the second conducting structure.
26. The method as claimed in claim 22 , wherein a process for forming the third conducting structure is different from that for forming the second conducting structure.
27. The method as claimed in claim 18 , wherein the integrated circuit device comprises a signal processor.
28. The method as claimed in claim 18 , wherein the first conducting structure is formed on the second substrate and extends onto the redistribution layer, and wherein the second conducting structure is formed on the first substrate.
29. The method as claimed in claim 18 , wherein the first conducting structure is formed on the second substrate and extends onto the redistribution layer, and wherein a fourth conducting structure is formed on the second substrate.
30. The method as claimed in claim 18 , wherein the first conducting structure is formed between the first substrate and the second substrate, and wherein the second conducting structure is formed on the first substrate.
31. The method as claimed in claim 18 , wherein the sensing device is adjacent to the first surface, and the second substrate is attached to the second surface, and wherein the first substrate further comprises a conducting pad adjacent to the first surface, and the redistribution layer is located on the second surface of the first substrate and is electrically connected to the conducting pad.
32. The method as claimed in claim 18 , wherein a material of the second conducting structure is different from that of the first conducting structure.
33. The method as claimed in claim 32 , wherein a size of the second conducting structure is greater than that of the first conducting structure.
34. The method as claimed in claim 18 , wherein a process for forming the second conducting structure is different from that for forming the first conducting structure.