IP Library Granted Patent US 9,391,066
Granted Patent B2
US 9,391,066 · App. 14/712,689 · Granted Jul 12, 2016

Semiconductor device

Inventors: Shinya Suzuki (Nanae-cho, JP); Kiichi Makuta (Tokyo, JP)
Assignee: Renesas Electronics Corporation
H01L27/0292H01L23/49811H01L24/10H01L24/13H01L24/14H01L27/0207H01L27/0248G02F1/13452H01L23/5329H01L23/53209H01L23/53238H01L2224/13099H01L2224/1412H01L2224/16H01L2924/01002H01L2924/0103H01L2924/0104H01L2924/01004H01L2924/01005H01L2924/01006H01L2924/01012H01L2924/01013H01L2924/01015H01L2924/01019H01L2924/01022H01L2924/01023H01L2924/01025H01L2924/01027H01L2924/01029H01L2924/01033H01L2924/01041H01L2924/01042H01L2924/01044H01L2924/01046H01L2924/01047H01L2924/01049H01L2924/01055H01L2924/01057H01L2924/01059H01L2924/01072H01L2924/01073H01L2924/01074H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/04941H01L2924/14H01L2924/15788H01L2924/30105
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Quick Facts
Patent No.
US 9,391,066
App. No.
14/712,689
Granted
Jul 12, 2016
Kind
B2
Abstract

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.

Claims (28)

1. A semiconductor device comprising:

(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;

(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;

(c) a plurality of input protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;

(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of input protection elements; and

(e) a plurality of input bump electrodes formed over the first insulating film, the plurality of input bump electrodes being arranged along a first long edge of the pair of long edges,

wherein the plurality of input bump electrodes are for receiving input signals from an external device,

wherein the plurality of input protection elements are electrically coupled between respective ones of the plurality of input bump electrodes and the internal circuit,

wherein the plurality of input bump electrodes include a first input bump electrode and a second input bump electrode,

wherein the plurality of input protection elements include a first input protection element and a second input protection element,

wherein the first input protection element electrically coupled to the first input bump electrode overlaps the first input bump electrode in a planar view, and

wherein the second input protection element electrically coupled to the second input bump electrode does not overlap the second input bump electrode in a planar view.

2. The semiconductor device according to claim 1 ,

wherein a third bump electrode is disposed so as to overlap parts of the plurality of MISFETs in a planar view.

3. The semiconductor device according to claim 1 ,

wherein the second input protection element is disposed at an inner side of the semiconductor substrate, further from the first long edge than the plurality of input bump electrodes, in a first direction along the pair of short edges of the semiconductor substrate in a planar view.

4. The semiconductor device according to claim 1 , further comprising:

(f) a plurality of output protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;

(g) a plurality of output bump electrodes formed over the first insulating film, the plurality of output bump electrodes being arranged along a second long edge of the pair of long edges,

wherein the plurality of output bump electrodes are for sending output signals to another external device, and

wherein the plurality of output protection elements are electrically coupled between respective ones of the plurality of output bump electrodes and the internal circuit.

5. The semiconductor device according to claim 4 , wherein the plurality of output protection elements overlap the plurality of output bump electrodes in a planar view.

6. The semiconductor device according to claim 4 , wherein the plurality of input bump electrodes are arranged linearly along the first long edge while the plurality of output bump electrodes are arranged in a staggered manner along the second long edge.

7. The semiconductor device according to claim 1 , wherein each of the plurality of input protection elements includes two diodes.

8. The semiconductor device according to claim 7 , wherein each of the plurality of output protection elements includes two diodes.

9. The semiconductor device according to claim 1 , wherein each of the plurality of input protection elements includes two transistors.

10. The semiconductor device according to claim 9 , wherein each of the plurality of output protection elements includes two transistors.

11. The semiconductor device according to claim 1 , wherein the semiconductor device is an LCD driver that drives a liquid crystal display device.

Assignments (1)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
Priority Claims (1)
JP 2009-173356 · Jul 24, 2009 · national
Continuity (3)
Continuation 14028755 · Sep 17, 2013
Division 12793431 · Jun 3, 2010
Related Publication 20150255452A1 · Sep 10, 2015