AUTO-TRACKING UNSELECTED WORD LINE VOLTAGE GENERATOR
Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
1 . A method for operating a non-volatile memory, comprising:
generating a plurality of unselected word line voltages using a replica adjustable resistance bit line structure, the replica adjustable resistance bit line structure includes a replica adjustable resistance local bit line and a replica select gate, the replica adjustable resistance local bit line is connected to a replica global bit line, the replica global bit line is set to a selected bit line voltage during a memory operation; and
performing the memory operation on a memory array, the memory array includes a first word line and a first global bit line, the first global bit line is connected to an adjustable resistance bit line structure that includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line, the memory array includes a plurality of unselected word lines, a plurality of unselected memory cells is arranged between the adjustable resistance local bit line and the plurality of unselected word lines, the memory operation includes applying a selected word line voltage to the first word line and applying the selected bit line voltage to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the memory operation includes applying the plurality of unselected word line voltages to the plurality of unselected word lines while the adjustable resistance local bit line is set into the conducting state.
2 . The method of claim 1 , wherein:
the replica adjustable resistance local bit line is connected to a replica memory cell and a plurality of other replica memory cells, a reference line connects to the replica memory cell and a plurality of other reference lines connects to the plurality of other replica memory cells; and
the generating a plurality of unselected word line voltages includes setting the replica global bit line to the selected bit line voltage and setting the reference line to the selected word line voltage.
3 . The method of claim 2 , wherein:
the generating a plurality of unselected word line voltages includes outputting a first voltage associated with a first reference line of the plurality of other reference lines; and
the memory operation includes applying the first voltage to a first unselected word line of the plurality of unselected word lines while the adjustable resistance local bit line is set into the conducting state.
4 . The method of claim 2 , wherein:
the generating a plurality of unselected word line voltages includes generating the plurality of unselected word line voltages based on locations of the plurality of other replica memory cells along the replica adjustable resistance local bit line.
5 . The method of claim 1 , wherein:
the generating a plurality of unselected word line voltages includes generating the plurality of unselected word line voltages such that the voltage stress across each of the plurality of unselected memory cells is substantially 0V during at least a portion of the memory operation.
6 . The method of claim 1 , wherein:
the generating a plurality of unselected word line voltages includes generating the plurality of unselected word line voltages based on a location of the first word line along the adjustable resistance local bit line.
7 . The method of claim 1 , further comprising:
setting a set of replica memory cells connected to the replica adjustable resistance local bit line into a high resistance state prior to generating the plurality of unselected word line voltages, the setting a set of replica memory cells includes performing a RESET operation on a first replica memory cell of the set of replica memory cells.
8 . The method of claim 1 , further comprising:
setting a set of replica memory cells connected to the replica adjustable resistance local bit line into a low resistance state prior to generating the plurality of unselected word line voltages, the setting a set of replica memory cells includes performing a SET operation on a first replica memory cell of the set of replica memory cells.
9 . The method of claim 1 , wherein:
the memory operation comprises a programming operation.
10 . The method of claim 1 , wherein:
the replica adjustable resistance local bit line comprises undoped polysilicon.
11 . The method of claim 1 , wherein:
the first memory cell comprises a ReRAM memory cell; and
the memory array comprises a three-dimensional memory array.
12 . A non-volatile storage system, comprising:
a memory array, the memory array includes a first adjustable resistance bit line structure, the first adjustable resistance bit line structure includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line, the memory array includes a plurality of unselected word lines, a plurality of unselected memory cells is arranged between the adjustable resistance local bit line and the plurality of unselected word lines;
an unselected word line voltage generator, the unselected word line voltage generator configured to generate a plurality of unselected word line voltages using a replica adjustable resistance bit line structure, the replica adjustable resistance bit line structure includes a replica adjustable resistance local bit line and a replica select gate, the replica adjustable resistance local bit line is connected to a replica global bit line, the replica global bit line is set to a selected bit line voltage during a memory operation; and
one or more managing circuits in communication with the first adjustable resistance bit line structure, the one or more managing circuits configured to cause a selected word line voltage to be applied to the first word line and the selected bit line voltage to be applied to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the one or more managing circuits configured to cause the plurality of unselected word line voltages to be applied to the plurality of unselected word lines while the adjustable resistance local bit line is set into the conducting state.
13 . The non-volatile storage system of claim 12 , wherein:
the replica adjustable resistance local bit line is connected to a replica memory cell and a plurality of other replica memory cells, a reference line connects to the replica memory cell and a plurality of other reference lines connects to the plurality of other replica memory cells, the unselected word line voltage generator configured to set the replica global bit line to the selected bit line voltage and configured to set the reference line to the selected word line voltage.
14 . The non-volatile storage system of claim 13 , wherein:
the unselected word line voltage generator outputs a first voltage associated with a first reference line of the plurality of other reference lines; and
the one or more managing circuits configured to cause the first voltage to be applied to a first unselected word line of the plurality of unselected word lines while the adjustable resistance local bit line is set into the conducting state.
15 . The non-volatile storage system of claim 13 , wherein:
the unselected word line voltage generator configured to generate the plurality of unselected word line voltages based on locations of the plurality of other replica memory cells along the replica adjustable resistance local bit line.
16 . The non-volatile storage system of claim 12 , wherein:
the unselected word line voltage generator configured to generate the plurality of unselected word line voltages such that the voltage stress across each of the plurality of unselected memory cells is substantially 0V during at least a portion of the memory operation.
17 . The non-volatile storage system of claim 12 , wherein:
the unselected word line voltage generator configured to generate the plurality of unselected word line voltages based on a location of the first word line along the adjustable resistance local bit line.
18 . The non-volatile storage system of claim 12 , wherein:
the replica adjustable resistance local bit line is connected to a set of replica memory cells, each memory cell of the set of replica memory cells is RESET prior to generating the plurality of unselected word line voltages.
19 . The non-volatile storage system of claim 12 , wherein:
the memory operation comprises a programming operation;
the replica adjustable resistance local bit line comprises undoped polysilicon;
the first memory cell comprises a ReRAM memory cell; and
the memory array comprises a three-dimensional memory array.
20 . An auto-tracking voltage generator, comprising:
a replica adjustable resistance bit line structure, the replica adjustable resistance bit line structure includes a replica adjustable resistance local bit line and a replica select gate, the replica adjustable resistance local bit line comprises undoped polysilicon, the replica adjustable resistance local bit line is connected to a replica global bit line, the replica adjustable resistance local bit line is connected to a replica memory cell and a plurality of other replica memory cells, a reference line connects to the replica memory cell and a plurality of other reference lines connects to the plurality of other replica memory cells;
a first analog multiplexor, the first analog multiplexor configured to set the reference line to a selected word line voltage while the replica global bit line is set to a selected bit line voltage; and
a second analog multiplexor, the second analog multiplexor configured to output a first reference voltage corresponding with a first reference line of the plurality of other reference lines while the replica global bit line is set to the selected bit line voltage.