Systems and methods for SRAM with backup non-volatile memory that includes MTJ resistive elements
View Patent ↗A memory device has an SRAM that stores a logic state. A first MTJ has two terminals. A second one of the terminals is coupled to a storing node. A first terminal of a second MTJ is coupled to the storing node. The first and second MTJs are programmed to a first resistance by flowing current from the first second terminals and to a second resistance by flowing current from the second to first terminal. A storing circuit is coupled to the storing node, the SRAM cell, and a non-volatile word line. The storing circuit couples the logic state of the SRAM cell to the storing node during a store mode. The logic state of the SRAM cell is stored in the first and second MTJs by applying a storing voltage between the first terminal of the first MTJ and the second terminal of the second MTJ of a first polarity then a second polarity.
1. A memory device, comprising:
an SRAM cell that stores a logic state;
a first MTJ having a first terminal and a second terminal coupled to a storing node;
a second MTJ having a first terminal and a second terminal, wherein the first terminal of the second MTJ is coupled to the storing node, and
wherein the first and second MTJs are characterized as being programmed to a first resistance state by flowing current from the first terminal to the second terminal and to a second resistance state, different from the first resistance state, by flowing current from the second terminal to the first terminal;
a storing circuit coupled to the storing node, the SRAM cell, and a non-volatile word line, wherein the storing circuit couples the logic state of the SRAM cell to the storing node during a store mode, wherein the storing circuit comprises:
a first P channel transistor having a control electrode coupled to a complementary non-volatile word line;
a second P channel transistor having a control electrode coupled to the SRAM cell;
a first N channel transistor having a control electrode coupled to the non-volatile word line; and
a second N channel transistor having a control electrode coupled to the SRAM cell;
wherein:
the first and second P channel transistors are coupled in series between a positive power supply terminal and the storing node; and
the first and second N channel transistors are coupled in series between a negative power supply terminal and the storing node;
wherein, during the store mode, the logic state of the SRAM cell is stored in the first and second MTJs by applying a storing voltage between the first terminal of the first MTJ and the second terminal of the second MTJ of a first polarity during a first time period of a store operation and a second polarity during a second time period of the store operation.
2. The memory device of claim 1 , wherein the storing circuit comprises a first transistor having a control electrode coupled to the non-volatile word line, a first current electrode coupled to the storing node, and a second current electrode coupled to the SRAM cell.
3. The memory device of claim 2 , wherein the SRAM cell is further characterized as having a first storage node and a second storage node and wherein the second current electrode of the first transistor is coupled to the second storage node.
4. The memory device of claim 3 , further comprising a restore circuit having an input coupled to the storing node and an output coupled to the first storage node.
5. The memory device of claim 4 , wherein the restore circuit comprises a second transistor having a control electrode coupled to the storing node, a first current electrode coupled to the first storage node, and a second current electrode coupled to a reference voltage.
6. The memory device of claim 3 , wherein the SRAM cell comprises a first pass gate coupled to a first bit line and the first storage node, a second pass gate coupled to a second bit line and the second storage node, a first inverter having an input coupled to the first storage node and an output coupled to the second storage node, and a second inverter having an input coupled to the second storage node and an output coupled to the first storage node, wherein the second pass gate is larger than the first pass gate and the first inverter is larger than the second inverter.
7. The memory device of claim 6 , wherein the first transistor is implemented as two transistors in parallel.
8. The memory device of claim 1 , wherein the negative power supply terminal comprises a ground terminal.
9. The memory device of claim 8 , wherein the SRAM cell is further characterized as having a first storage node and a second storage node and wherein the control electrodes of the second P channel transistor and the second N channel transistor are coupled to the first storage node.
10. The memory device of claim 9 , further comprising a restore circuit having an input coupled to the storing node and an output coupled to the first storage node.
11. The memory device of claim 10 , wherein the restore circuit comprises a data transistor having a control electrode coupled to the storing node, a first current electrode coupled to the first storage node, and a second current electrode coupled to a reference voltage.
12. The memory device of claim 11 , wherein the SRAM cell comprises a first pass gate coupled to a first bit line and the first storage node, a second pass gate coupled to a second bit line and the second storage node, a first inverter having an input coupled to the first storage node and an output coupled to the second storage node, and a second inverter having an input coupled to the second storage node and an output coupled to the first storage node, wherein the first and second pass gates are the same size and the first and second inverters are the same size.
13. A method of operating a memory device, wherein the memory device comprises
an SRAM cell that stores a logic state;
a first MTJ having a first terminal and a second terminal coupled to a storing node;
a second MTJ having a first terminal and a second terminal, wherein the first terminal of the second MTJ is coupled to the storing node, and
wherein the first and second MTJs are characterized as being programmed to a first resistance state by flowing current from the first terminal to the second terminal and to a second resistance state, different from the first resistance state, by flowing current from the second terminal to the first terminal;
the method comprising:
coupling the logic state of the SRAM cell to the storing node during a store mode;
applying a storing voltage between the first terminal of the first MTJ and the second terminal of the second MTJ of a first polarity during a first time period of a store operation and a second polarity during a second time period of the store operation; and
restoring a logic state present on the storing node to the SRAM cell by writing a predetermined logic state into the SRAM cell and coupling a storage node of the SRAM cell to a reference voltage if the logic state of the storing node is different from the predetermined logic state.
14. The method of claim 13 , wherein the memory device is further characterized by the SRAM cell storing a true logic state and a complementary logic state, the method further characterized by coupling the true logic from the SRAM cell to the storing node.
15. The method of claim 13 , wherein the memory device is further characterized by the SRAM cell storing a true logic state and a complementary logic state, the method further characterized by inverting the complementary logic and coupling the inverted complementary logic state to the storing node.
16. The method of claim 15 , wherein the inverting the complementary logic and coupling the inverted complementary logic state to the storing node results in providing a buffered signal to the storing node.
17. A memory device, comprising:
an SRAM cell that stores a logic state in a true storage node and a complementary storage node;
a first MTJ having a first terminal and a second terminal coupled to a storing node;
a second MTJ having a first terminal and a second terminal, wherein the first terminal of the second MTJ is coupled to the storing node, and
wherein the first and second MTJs are characterized as being programmed to a first resistance state by flowing current from the first terminal to the second terminal and to a second resistance state, different from the first resistance state, by flowing current from the second terminal to the first terminal;
a storing circuit coupled to the storing node, to one of the group consisting of the true storage node and the complementary storage node, and a non-volatile word line, wherein the storing circuit couples the logic state of the SRAM cell to the storing node during a store mode by direct coupling when coupled to the true storage node and inverting when coupled to the complementary storage node;
a restore circuit including a transistor having a control electrode coupled to the storing node, a first current electrode coupled to the true storage node, and a second current electrode coupled to a reference voltage;
wherein, during the store mode, the logic state of the SRAM cell is stored in the first and second MTJs by applying a storing voltage between the first terminal of the first MTJ and the second terminal of the second MTJ of a first polarity during a first time period of a store operation and a second polarity during a second time period of the store operation.