Translation lookaside buffer in memory
Examples of the present disclosure provide apparatuses and methods related to a translation lookaside buffer in memory. An example method comprises receiving a command including a virtual address from a host translating the virtual address to a physical address on volatile memory of a memory device using a translation lookaside buffer (TLB).
1. A method, comprising:
receiving a command including a number of virtual addresses from a host at a memory device that includes a logic base, and a number of memory arrays, and a number of vaults, wherein:
each of the number of vaults includes a partition of memory from each of the number of memory arrays: and
each of the number of vaults is functionally and operationally independent of other vaults:
translating the number of virtual addresses to a number of physical addresses using a translation lookaside buffer (TLB) located on a switch of a logic base, wherein:
the logic base is located on the memory device; and
the switch is configured to provide availability of collective bandwidth from the number of vaults to the host;
sending the number of translated physical addresses to one of the number of memory arrays; and
locating the physical addresses in the memory device: and
using the collective bandwidth to access the number of memory vaults substantially simultaneously.
2. The method of claim 1 , wherein the method includes receiving the command via a bus from the host to the memory device.
3. The method of claim 1 , wherein translating the number of virtual addresses to the number of physical addresses includes translating the number of virtual addresses to a number of physical addresses on a hybrid memory cube (HMC).
4. The method of claim 1 , wherein translating the number of virtual addresses to the number of physical addresses includes translating the number of virtual addresses to a number of physical addresses on a processor in memory (PIM) device.
5. The method of claim 1 , wherein the method includes updating the TLB by remapping a relationship between virtual and physical addresses in response to data in the memory device being moved.
6. The method of claim 1 , wherein translating the number of virtual addresses to the number of physical addresses includes a translation that only includes bits associated with the number of physical addresses on the memory device.
7. The method of claim 1 , wherein translating includes using the TLB that is located in a controller of the memory device.
8. The method of claim 1 , wherein translating includes using the TLB that is located in a respective memory array of the number of memory arrays.
9. The method of claim 1 , wherein translating includes using the TLB that is located in a logic base of the memory device.
10. The method of claim 1 , wherein translating includes using the TLB to map the number of virtual addresses directly to the number of physical addresses on the memory device.
11. The method of claim 1 , wherein the method includes using the memory device to translate the number of virtual addresses to a number of physical addresses.
12. An apparatus, comprising:
a number of memory arrays including a number of vaults, wherein:
each of the number of vaults includes a partition of memory from each of the number of memory arrays; and
each of the number of vaults is functionally and operationally independent of other vaults; and
a logic base, on which the number of memory arrays are stacked on the logic base and including a number of controllers, wherein:
each of the number of controllers is coupled to a respective vault of the number of vaults, and configured to control the respective vault of the number of vaults; and
the logic base includes a translation lookaside buffer (TLB) located on a switch of the logic base, wherein the switch is coupled to the number of controllers and configured to:
use the TLB to translate a number of virtual addresses from a command to a number of physical addresses in the memory array using the TLB; and
provide availability of collective internal bandwidth from the number of vaults to a host, wherein the collective internal bandwidth is used to access the number of vaults substantially simultaneously.
13. The apparatus of claim 12 , wherein the controller is configured to receive the command from the host on a bus.
14. The apparatus of claim 12 , wherein the number of physical addresses of the memory array includes each addressable physical address of the memory array.
15. The apparatus of claim 12 , wherein the apparatus is a processor in memory (PIM) device.
16. A method, comprising:
receiving a command including a number of virtual addresses from a host to a memory device via a bus, wherein the memory device includes a number of memory arrays, which include a number of vaults, wherein:
each of the number of vaults includes a partition of memory from each of the number of memory arrays: and
each of the number of vaults is functionally and operationally independent of other vaults:
translating the number of virtual addresses to a number of physical addresses using a translation lookaside buffer (TLB), wherein:
the TLB is located on a switch of a logic base, which is located on the memory device; and
the switch is configured to provide availability of collective internal bandwidth from the number of vaults to the host, wherein the collective internal bandwidth is used to access the number of vaults substantially simultaneously; and
sending the translated physical addresses to a memory array of the memory device.
17. The method of claim 16 , wherein the method includes creating the command that includes the number of virtual addresses with a processor on the host.
18. The method of claim 16 , wherein translating the number of virtual addresses to the number of physical addresses occurs on the memory device side of the bus.
19. An apparatus, comprising:
a number of memory arrays, each of the number of memory arrays including a number of vaults, wherein:
each of the number of vaults includes a partition of memory from each of the number of memory arrays; and
each of the number of vaults is functionally and operationally independent of other vaults; and
a logic base, on which the number of memory arrays are stacked, wherein the logic base is coupled to the number of memory arrays and includes a translation lookaside buffer (TLB) that is located on a switch of the logic base, and wherein:
the logic base is configured to receive a command and translate a number of virtual addresses from the command to a number of physical addresses in the number of memory arrays using the TLB; and
the switch is configured to provide an availability of collective bandwidth from the number of vaults to a host, wherein the collective bandwidth is used to access the number of memory arrays substantially simultaneously.
20. The apparatus of claim 19 , wherein the apparatus is a hybrid memory cube (HMC).
21. The apparatus of claim 19 , wherein the logic base is coupled to the host that includes a processor and wherein the logic base is configured to receive the command from the host.
22. The apparatus of claim 19 , wherein the TLB is configured to map the number of virtual addresses to each of the number of physical addresses in the number of memory arrays.
23. An apparatus, comprising:
a host;
a logic base; and
a number of memory devices coupled to the host via a logic base, wherein the number of memory devices include a number of vaults, and wherein:
each of the number of vaults includes a partition of memory from each of the number of memory devices; and
each of the number of vaults is functionally and operationally independent of other vaults; and
the logic base including a number of controllers and a translation lookaside buffer (TLB) located on a switch of the logic base; wherein each controller of the number of controllers is configured to control a vault of the number of vaults of a respective one of the number of memory devices independently of the other of the number of vaults, wherein:
each of the number of memory devices are configured to receive a command including a number of virtual addresses from the host; and
the switch coupled to the number of controllers and the host is configured to:
translate the virtual addresses to a number of physical addresses on the number of volatile memory devices, wherein the number of translated physical addresses is sent to a memory array of a corresponding memory device; and
provide availability of collective internal bandwidth from the number of vaults to the host, wherein the collective bandwidth is used to access the number of vaults substantially simultaneously.
24. The apparatus of claim 23 , wherein the number of memory devices include a hybrid memory cube (HMC), a processor in memory (PIM) device, and a flash memory device.
25. The apparatus of claim 23 , wherein the host is configured to create a number of commands that include the number of virtual addresses that are sent to the number of memory devices.
26. The apparatus of claim 25 , wherein each of the number of memory devices are configured to use their respective TLBs to translate no more than a number of bits to identify the number of physical addresses on their respective memory devices.