Granted Patent B2

US 10,157,093 · App. 14/722,632 · Granted Dec 18, 2018

Abstract

Claims (32)

1. A memory system, comprising:

a memory array, wherein the memory array comprises a first section having a first plurality of programmed bitcells having a first threshold voltage distribution and a second section having a second plurality of programmed bitcells having a second threshold voltage distribution which has a lower average threshold voltage than the first threshold voltage distribution, wherein the first plurality of programmed bitcells are programmed with a first N-bit data value using a first program verify level and second plurality of programmed bitcells are programmed with a second N-bit data value using a second program verify level different from the first program verify level, wherein the first N-bit data value and the second N-bit data value have identical bit values at corresponding bit positions;

control circuitry configured to provide a read request to the memory array and receive read data in response to the read request, wherein the read data comprises first read data from the first plurality of programmed bitcells and second read data from the second plurality of bitcells; and

comparator circuitry configured to compare the first read data to the second read data and generate an error indicator in response to the compare, wherein the error indicator indicates an impending failure of the memory system.

2. The memory system of claim 1 , wherein each of the first N-bit data value and the second N-bit data value include execute control code and reference data.

3. The memory system of claim 2 , wherein the control circuitry is configured to use the execute control code and reference data to configure the memory array upon a reset of the memory system.

4. The memory system of claim 1 , wherein the comparator circuitry performs a bit-wise compare of each bit in the first read data to a corresponding bit of the second read data.

5. The memory system of claim 4 , wherein the comparator circuitry is configured to assert the error indicator in response to a mismatch occurring in the bit-wise compare.

6. The memory system of claim 5 , further comprising an error log configured to store an address of the first read data when the error indicator is asserted.

7. The memory system of claim 4 , wherein the memory controller is configured to perform a refresh of the first and second plurality of programmed bitcells of the memory array if a mismatch occurs in the bit-wise compare.

8. The memory system of claim 7 , wherein the first section further includes a refresh indicator corresponding to the first read data, wherein the memory controller is configured to assert the refresh indicator in response to performing the refresh.

9. The memory system of claim 1 , wherein the first section further comprises error correction code bits corresponding to the first read data, wherein the comparator circuitry is configured to correct the read data with the error correction code bits prior to comparing the first read data to the second read data.

10. The memory system of claim 1 , wherein the memory array comprises a user partition and a manufacturer defined information partition wherein the manufacturer defined information partition comprises the first section and the second section.

11. The memory system of claim 1 , wherein the first read data is characterized as production data and the second read data is characterized as margin data.

12. A method for generating an error indicator in a memory system, comprising:

performing a read access to a memory array to obtain first read data and second read data from the memory array, wherein the first read data corresponds to a first N-bit value programmed with a first program verify level and the second read data corresponds to a second N-bit value programmed with a second program verify level different from the first program verify level, wherein the first N-bit data value and the second N-bit data value have identical bit values at corresponding bit positions;

performing a bit-wise comparison of the first read data with the second read data; and

in response to a mismatch occurring in the bit-wise comparison, refreshing the memory array, wherein the mismatch occurring indicates an impending failure of the memory system.

13. The method of claim 12 , wherein performing the read access to the memory array to obtain the first read data and the second read data is performed using a same read verify level for the first read data and the second read data.

14. The method of claim 12 , wherein the same set of programmed data values comprises execute control code and reference data.

15. The method of claim 12 , wherein performing the read access further obtains error correction code bits corresponding to the first read data, wherein the method further comprises:

using the error correction code bits to correct the first read data prior to performing the bit-wise comparison.

16. The method of claim 12 , further comprising:

in response to refreshing the memory array, asserting a refresh indicator corresponding to the first and second read data.

17. The method of claim 16 , further comprising:

performing an integrity check of the memory array, wherein performing the read access and performing the bit-wise comparison is repeated for each location within a predetermined partition of the memory array.

18. A memory system, comprising:

a nonvolatile memory array, wherein the memory array comprises a first section having a first plurality of programmed bitcells having a first threshold voltage distribution and a second section having a second plurality of programmed bitcells having a second threshold voltage distribution which has a lower average threshold voltage than the first threshold voltage distribution, wherein the first plurality of programmed bitcells is programmed with a first N-bit value of execute control code and reference data using a first program verify level, wherein the second plurality of programmed bitcells is programmed with a second N-bit value of execute control code and reference data using a second program verify level different from the first program verify level, and wherein the first N-bit data value and the second N-bit data value have identical bit values at corresponding bit positions;

control circuitry configured to provide a read request to the memory array and receive read data in response to the read request, wherein the read data comprises first read data from the first section and second read data from the second section, wherein the control circuitry is configured to use the execute control code and reference data to configure the memory array upon a reset of the memory system; and

comparator circuitry coupled to compare each bit of the first read data to a corresponding bit of the second read data, wherein the control circuitry is configured to perform a refresh of the first read data and the second read data when a mismatch occurs, wherein the mismatch occurring indicates an impending failure of the memory system.

19. The memory system of claim 18 , wherein the first section further includes a refresh indicator corresponding to the first read data, wherein the memory controller is configured to assert the refresh indicator in response to performing the refresh.

20. The memory system of claim 18 , wherein the first section further comprises error correction code bits corresponding to the first read data, wherein the comparator circuitry is configured to correct the read data with the error correction code bits prior to comparing the first read data to the second read data.

Assignments (9)