Granted Patent B2

US 9,612,894 · App. 14/727,020 · Granted Apr 4, 2017

Abstract

Claims (28)

1. A method for high occurrence rate detection of interrupts comprising:

incrementing a count by a first number in response to at least one interrupt;

decrementing the count by a second number in response to a clock if the count is greater than zero;

determining an interrupt rate from the count; and

updating a fault collection unit (FCU) when the interrupt rate exceeds a threshold.

2. The method of claim 1 further comprising combining a plurality of interrupt lines to form the at least one interrupt.

3. The method of claim 2 further comprising enabling at least one of the plurality of interrupt lines with a mask configuration register.

4. The method of claim 1 further comprising dividing the clock by a clock division factor to reduce a rate by which the second number is decremented.

5. The method of claim 1 further comprising, storing by the FCU, at least one of the first number, the second number, a plurality of interrupt lines, a mask configuration register, a clock division factor, and the threshold.

6. The method of claim 1 further comprising resetting the count to zero after updating the FCU.

7. The method of claim 1 wherein updating the FCU sets a status bit in response to an early warning.

8. The method of claim 1 wherein updating the FCU sets a status bit in response to a severe alarm.

9. The detector of claim 1 wherein updating the FCU results in at least one of disabling a peripheral, disabling an interrupt, changing an interrupt routing and reconfiguring a device or software to a different operating mode.

10. A detector for high frequency interrupts comprising:

a counter configured to increment a count by a first number in response to at least one interrupt, and decrement the count by a second number in response to a clock if the count is greater than zero; and

a threshold detector configured to update a fault collection unit (FCU) when an interrupt rate determined from the count exceeds a threshold.

11. The detector of claim 10 further comprising a collector configured to combine a plurality of interrupt lines to form the at least one interrupt.

12. The detector of claim 11 further comprising a mask configuration register configured to enable at least one of the plurality of interrupt lines.

13. The detector of claim 10 wherein the at least one interrupt is responsive to a request from a communication port of a processor.

14. The detector of claim 10 wherein the at least one interrupt is responsive to a request from a peripheral of a processor.

15. The detector of claim 10 wherein the at least one interrupt is responsive to a request between two virtual machines.

16. The detector of claim 10 wherein the counter is configured to reset to zero after updating the FCU.

17. The detector of claim 10 further comprising a clock configuration register configured to divide the clock by a clock division factor to reduce a rate by which the second number is decremented.

18. The detector of claim 10 wherein the first number is stored in a configurable first register.

19. The detector of claim 10 wherein the threshold is stored in a configurable threshold register.

20. A detector for high frequency interrupts comprising:

a device configured to count a difference of a first number of at least one interrupt scaled by a first configurable factor and a second number of a plurality of clock transitions divided by a second configurable factor, a collector configured to combine a plurality of interrupt lines to form the at least one interrupt, a mask configuration register configured to enable at least one of the plurality of interrupt lines; and

a threshold detector configured to update a fault collection unit (FCU) when the difference exceeds a configurable threshold.

Assignments (15)