Method and apparatus for limiting access to an integrated circuit (IC)
View Patent ↗A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.
1. An integrated circuit (IC) comprising:
a voltage detector for detecting tampering with a power supply voltage of the IC; and
a temperature detector for detecting tampering with a temperature of the IC, wherein a combined average power consumption of the voltage detector and the temperature detector is less than five microwatts.
2. The IC of claim 1 further comprising:
a clock detector for detecting an abnormal clock signal, wherein a total combined average power consumption of the voltage detector, the temperature detector, and the clock detector is less than five microwatts.
3. The IC of claim 2 wherein the clock detector comprises:
a stopped clock detector for detecting a clock signal being stopped.
4. The IC of claim 3 wherein the stopped clock detector further comprises:
a clock stopped low detector to detect if the clock signal at a node of the IC is abnormal by virtue of the clock signal being stopped at a low logic level; and
a clock stopped high detector to detect if the clock signal at the node is abnormal by virtue of the clock signal being stopped at a high logic level.
5. The IC of claim 2 wherein the clock detector comprises:
a slow clock detector for detecting when a clock frequency of a clock signal at the IC is abnormal by virtue of being slower than a specified lower clock frequency limit independent of a duty cycle of the clock signal.
6. The IC of claim 2 wherein the clock detector comprises:
a fast clock detector for detecting when a clock frequency of a clock signal at the IC is abnormal by virtue of being faster than a specified upper clock frequency limit independent of a duty cycle of the clock signal.
7. The IC of claim 2 wherein the clock detector further comprises:
an abnormal duty cycle detector to detect if the clock signal at a node of the IC is abnormal by virtue of the clock signal having a duty cycle that is outside of a specified duty cycle range.
8. The IC of claim 1 wherein the IC limits access to the IC in response to detection of tampering, wherein limiting the access comprises at least one of: inhibiting an external signal line of the IC, inhibiting execution of an instruction in the IC, resetting at least a portion of the IC, disabling reading of at least a portion of a memory array of the IC, and disabling execution of instructions stored in at least a portion of the memory array of the IC.
9. A method, at an integrated circuit (IC), comprising:
detecting, using a voltage detector of the IC, tampering with a power supply voltage of the IC; and
detecting, using a temperature detector of the IC, tampering with a temperature of the IC, wherein a combined average power consumption of the voltage detector and the temperature detector is less than five microwatts.
10. The method of claim 9 further comprising:
detecting, using a clock detector of the IC, an abnormal clock signal, wherein a total combined average power consumption of the voltage detector, the temperature detector, and the clock detector is less than five microwatts.
11. The method of claim 10 wherein the detecting, using the clock detector of the IC, the abnormal clock signal comprises:
detecting, using a stopped clock detector of the IC, a clock signal being stopped.
12. The method of claim 11 wherein detecting, using the stopped clock detector of the IC, the clock signal being stopped comprises:
detecting, using a clock stopped low detector of the IC, when the clock signal at a node of the IC is abnormal by virtue of the clock signal being stopped at a low logic level; and
detecting, using a clock stopped high detector of the IC, when the clock signal at the node is abnormal by virtue of the clock signal being stopped at a high logic level.
13. The method of claim 10 wherein the detecting, using the clock detector of the IC, the abnormal clock signal comprises:
detecting, using a slow clock detector of the IC, when a clock frequency of a clock signal at the IC is abnormal by virtue of being slower than a specified lower clock frequency limit independent of a duty cycle of the clock signal.
14. The method of claim 10 wherein the detecting, using the clock detector of the IC, the abnormal clock signal comprises:
detecting, using a fast clock detector of the IC, when a clock frequency of a clock signal at the IC is abnormal by virtue of being faster than a specified upper clock frequency limit independent of a duty cycle of the clock signal.
15. The method of claim 10 wherein the detecting, using the clock detector of the IC, the abnormal clock signal comprises:
detecting, using an abnormal duty cycle detector of the IC, when the clock signal at a node of the IC is abnormal by virtue of the clock signal having a duty cycle that is outside of a specified duty cycle range.
16. The method of claim 9 further comprising:
limiting, by the IC, access to the IC in response to detection of tampering, wherein the limiting the access comprises at least one of: inhibiting an external signal line of the IC, inhibiting execution of an instruction in the IC, resetting at least a portion of the IC, disabling reading of at least a portion of a memory array of the IC, and disabling execution of instructions stored in at least a portion of the memory array of the IC.
17. An integrated circuit (IC) comprising:
a voltage detector for detecting tampering with a power supply voltage of the IC;
a temperature detector for detecting tampering with a temperature of the IC, wherein a combined average power consumption of the voltage detector and the temperature detector is less than five microwatts; and
a tamper detector controller, the tamper detector controller coupled to the voltage detector and to the temperature detector, the tamper detector controller for limiting access to the IC in response to detection of tampering, wherein limiting the access comprises at least one of: inhibiting an external signal line of the IC, inhibiting execution of an instruction in the IC, resetting at least a portion of the IC, disabling reading of at least a portion of a memory array of the IC, and disabling execution of instructions stored in at least a portion of the memory array of the IC.
18. The IC of claim 17 further comprising:
a clock detector for detecting an abnormal clock signal, the clock detector coupled to the tamper detector controller, wherein a total combined average power consumption of the voltage detector, the temperature detector, and the clock detector is less than five microwatts.
19. The IC of claim 17 wherein the clock detector comprises:
a stopped clock detector for detecting a clock signal being stopped.
20. The IC of claim 17 further comprising:
a sampled bandgap reference coupled to the temperature detector, the temperature detector referring to an output of the sampled bandgap reference to determine the temperature of the IC.