IP Library Granted Patent US 9,583,525
Granted Patent B2
US 9,583,525 · App. 14/728,111 · Granted Feb 28, 2017

Die stacked image sensors and related methods

Inventors: Swarnal Borthakur (Boise, ID); Marc Sulfridge (Boise, ID); Vladimir Korobov (San Mateo, CA)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L27/14634H01L27/1463H01L27/1469H01L27/14627H01L27/14632H01L27/14636H01L27/14685H01L27/14687
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Quick Facts
Patent No.
US 9,583,525
App. No.
14/728,111
Granted
Feb 28, 2017
Kind
B2
Abstract

An image sensor. Implementations may include: a first die including a plurality of pixels; a second die including a plurality of transistors, capacitors, or both transistors and capacitors; a third die including analog circuitry, logic circuitry, or analog and logic circuitry. The first die may be hybrid bonded to the second die, and the second die may be fusion bonded to the third die. The plurality of transistors, capacitors or transistors and capacitors of the second die may be adapted to enable operation of the plurality of pixels of the first die. The analog circuitry, logic circuitry, and analog circuitry and logical circuitry may be adapted to perform signal routing.

Claims (10)

1. A method of manufacturing an image sensor, the method comprising:

hybrid bonding a first wafer comprising a plurality of first die with a second wafer comprising a plurality of second die;

thinning the second wafer;

hybrid bonding the second wafer with a third wafer comprising a plurality of third die;

exposing a plurality of studs comprised in the second wafer;

wherein the plurality of first die each comprise a plurality of detectors adapted to convert photons to electrons;

wherein the plurality of second die each comprise a plurality of one of transistors, passive electrical components, and both transistors and passive electrical components; and

wherein the plurality of third die each comprise one of analog circuitry, logic circuitry, and analog circuitry and logic circuitry.

2. The method of claim 1 , wherein the plurality of second die are electrically coupled with the plurality of third die.

3. The method of claim 1 , further comprising forming a plurality of microlenses on a surface of the plurality of the detectors adapted to convert photons to electrons of each of the plurality of first die.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2015
From: BORTHAKUR, SWARNAL; SULFRIDGE, MARC; KOROBOV, VLADIMIR
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 035763/0838 →
Continuity (1)
Related Publication 20160358966A1 · Dec 8, 2016