Devices and methods of forming unmerged epitaxy for FinFET device

1. A method comprising:

obtaining a wafer having at least one source, at least one drain, and at least one fin;

exposing at least a portion of the at least one fin;

forming at least one sacrificial gate structure;

forming a first layer of an epitaxial growth on the at least one fin, wherein the first layer of epitaxial growth comprises a first side and a second side; and

depositing a first interlayer dielectric layer over the wafer;

planarizing the first interlayer dielectric layer;

exposing at least a portion of the first layer of an epitaxial growth, wherein exposing at least a portion of the first layer of epitaxial growth includes etching away a portion of the first layer of epitaxial growth to form a top surface of the first layer of epitaxial growth and an unexposed portion of the first side and an unexposed portion of the second side, the unexposed portions of the first and second sides contacting the first interlayer dielectric layer;

forming at least one second layer of an epitaxial growth on the first layer of an epitaxial growth, wherein the at least one second layer of epitaxial growth comprises a bottom surface, a first side surface, and a second side surface;

depositing at least one barrier layer over the at least one second layer of an epitaxial growth and the first interlayer dielectric layer, wherein the at least one barrier layer directly contacts the first side surface and the second side surface of the at least one second layer of epitaxial growth; and

depositing at least one flowable oxide layer over the wafer, wherein the at least one flowable oxide layer directly contacts the at least one barrier layer.

2. The method of claim 1 , wherein the first layer of an epitaxial growth substantially takes on a shape of a diamond.

3. The method of claim 1 , wherein the at least one second layer of an epitaxial growth substantially takes on a shape of at least one of a diamond, a square, a rectangle, a pentagon, a trapezoid, and a polygon.

4. The method of claim 1 , wherein the first layer of an epitaxial growth is conformally formed over the at least one fin.

5. The method of claim 1 , further comprising:

planarizing the at least one flowable oxide layer;

performing replacement metal gate process on the at least one sacrificial gate structure;

depositing at least one second interlayer dielectric layer over the at least one flowable oxide layer;

performing lithography to the at least one second interlayer dielectric layer; and

exposing at least a portion of the at least one second layer of an epitaxial growth.

6. The method of claim 5 , further comprising:

forming a first contact region over the at least one source and a second contact region over the at least one drain.

7. The method of claim 5 , wherein the at least one barrier layer is a contact etch stop layer.

8. The method of claim 7 , wherein the contact etch stop layer comprises:

nitride; and

low k material.

9. The method of claim 5 , further comprising:

depositing the at least one barrier layer over the first interlayer dielectric layer.

10. A method comprising:

obtaining a wafer having at least one source, at least one drain, and at least one fin;

exposing at least a portion of the at least one fin;

forming at least one sacrificial gate structure;

forming a first layer of an epitaxial growth on the at least one fin, wherein the first layer of epitaxial growth comprises at least a first side and a second side;

depositing a first interlayer dielectric layer over the wafer;

planarizing the first interlayer dielectric layer;

exposing at least a portion of the first layer of an epitaxial growth, wherein exposing at least a portion of the first layer of epitaxial growth includes etching away a portion of the first layer of epitaxial growth to form a top surface of the first layer of epitaxial growth, an exposed portion of the first side, and an exposed portion of the second side, and wherein the exposed portions of the first and second sides are positioned above the first interlayer dielectric layer;

forming a second layer of an epitaxial growth on the first layer of epitaxial growth, wherein the second layer of epitaxial growth comprises at least a third side and a fourth side;

depositing a second interlayer dielectric layer over the wafer;

planarizing the second interlayer dielectric layer;

exposing at least a portion of the second layer of epitaxial growth, wherein exposing at least a portion of the second layer of epitaxial growth includes etching away a portion of the second layer of epitaxial growth to form a top surface of the second layer of epitaxial growth, an exposed portion of the third side, and an exposed portion of the fourth side, and wherein the exposed portions of the third and fourth sides of the second layer of epitaxial growth are positioned above the second interlayer dielectric layer;

forming at least one third layer of an epitaxial growth on the second layer of epitaxial growth, wherein the third layer of epitaxial growth comprises at least a fifth side and a sixth side; and depositing at least one barrier layer over at least a portion of the at least one third layer of epitaxial growth, wherein the at least one barrier layer directly contacts the fifth side and the sixth side of the at least one third layer of epitaxial growth.

11. The method of claim 10 , further comprising:

depositing a first flowable oxide layer over the at least one barrier layer;

planarizing the first flowable oxide layer;

exposing at least a portion of the at least one third layer of an epitaxial growth; and

forming a first contact region over the at least one source and a second contact region over the at least one drain.

12. The method of claim 10 , wherein the at least one third layer of an epitaxial growth substantially takes on a shape of at least one of a diamond, a square, a rectangle, a pentagon, a trapezoid, and a polygon.

13. The method of claim 11 , wherein depositing the at least one barrier layer over the at least one third layer of an epitaxial growth includes depositing the at least one barrier layer over at least a portion of the second interlayer dielectric layer.

14. The method of claim 11 , wherein the at least one barrier layer is a contact etch stop layer comprising:

nitride; and

low k material.