Structure and formation method of chip package structure
A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.
1. A chip package structure, comprising:
a first package, wherein the first package comprises:
at least a semiconductor die;
a dielectric structure surrounding the semiconductor die;
a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die;
a second dielectric structure surrounding the semiconductor die, wherein the dielectric structure surrounds the second dielectric structure:
an interposer substrate over the first package, the interposer substrate having a bottom surface facing the first package, an opposing top surface facing away from the first package, and a plurality of conductive features providing electrical connections between the top surface and the bottom surface of the interposer substrate; and
a second package over the top surface of the interposer substrate, wherein the first package electrically couples the second package through the conductive structures and the conductive features, and the interposer substrate is between the second package and a top-most surface of the dielectric structure of the first package;
wherein the conductive structures completely penetrate through the dielectric structure, with ends of the conductive structures terminating at corresponding exterior surfaces of the dielectric structure,
wherein materials of the dielectric structure and the second dielectric structure are different from each other and wherein the interposer substrate is spaced from the first package by only a plurality of conductive elements between the interposer substrate and the first package.
2. The chip package structure as claimed in claim 1 , wherein the interposer substrate is separated from the first package.
3. The chip package structure as claimed in claim 2 , further comprising a plurality of conductive elements between the interposer substrate and the first package, wherein each of the conductive elements is electrically connected to at least one of the conductive structures.
4. The chip package structure as claimed in claim 3 , wherein the conductive elements comprise a solder material.
5. The chip package structure as claimed in claim 3 , wherein the conductive elements comprise copper pillars.
6. The chip package structure as claimed in claim 3 , further comprising an underfill material between the interposer substrate and the first package, and surrounding the conductive elements.
7. The chip package structure as claimed in claim 3 , wherein the interposer substrate is separated from the second package.
8. The chip package structure as claimed in claim 7 , further comprising a plurality of second conductive elements between the interposer substrate and the second package, wherein each of the second conductive elements is electrically connected to at least one of the conductive structures.
9. The chip package structure as claimed in claim 8 , wherein the second conductive elements comprise a solder material.
10. The chip package structure as claimed in claim 8 , further comprising a second underfill material between the interposer substrate and the second package and surrounding the second conductive elements.
11. The chip package structure as claimed in claim 1 , wherein the second package comprises at least one memory device.
12. The chip package structure as claimed in claim 1 , wherein the first package comprises at least one logic device.
13. The chip package structure as claimed in claim 1 , wherein the dielectric structure comprises a molding compound material.
14. The chip package structure as claimed in claim 1 , wherein the second dielectric structure comprises a molding compound material.
15. The chip package structure as claimed in claim 1 , further comprising a redistribution layer under the dielectric structure, the conductive structures, and the semiconductor die.
16. A method for forming a package structure; comprising:
providing a first package, wherein the first package comprises:
at least a semiconductor die;
a dielectric structure surrounding the semiconductor die;
a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die; and
a second dielectric structure surrounding the semiconductor die, wherein the dielectric structure surrounds the second dielectric structure;
bonding an interposer substrate over the first package, the interposer substrate having a bottom surface facing the first package, an opposing top surface facing away from the first package, and a plurality of conductive features providing electrical connections between the top surface and the bottom surface of the interposer substrate; and
bonding a second package over the top surface of the interposer substrate such that the interposer substrate is between the second package and a top-most surface of the dielectric structure of the first package;
wherein the conductive structures completely penetrate through the dielectric structure, with ends of the conductive structures terminating at corresponding exterior surfaces of the dielectric structure,
wherein materials of the dielectric structure and the second dielectric structure are different from each other and wherein the interposer substrate is spaced from the first package by only a plurality of conductive elements between the interposer substrate and the first package.
17. The method for forming a package structure as claimed in claim 16 , wherein the interposer substrate is bonded over the first package by a plurality of first conductive elements, and the second package is bonded over the interposer substrate by a plurality of second conductive elements.