Non-volatile random access memory (NVRAM)
View Patent ↗A non-volatile memory device includes an array of non-volatile (NV) memory cells organized in pairs. Each pair is included with a transistor to form a memory unit. Each unit is coupled to a bit line, a word line, and a pair of source lines. The NV elements are programmable to either a relatively high resistance or relatively low resistance and the particularly resistance is established, by converting one resistance type to the other or maintaining the existing resistance type the direction of current through the NV element. A bit is formed from two NV cells in different memory units which are programmed to different resistance types and thereby provide a differential pair from which the logic state of the bit can be determined.
1. A non-volatile (NV) memory device comprising:
a true bit line and a complementary bit line;
a first word line;
a plurality of NV memory elements comprising a first NV memory element, a second NV memory element, a third NV memory element, and a fourth NV memory element, wherein each of the first, second, third, and fourth NV memory elements are characterized as having a first terminal and second terminal, wherein a higher resistance state is established by providing a write current from the first terminal to the second terminal and a lower resistance state is established by providing a write current from the second terminal to the first terminal;
a first transistor having a first current electrode coupled to the true bit line, a control electrode coupled to the first word line, and a second current electrode coupled to the first terminal of the first NV memory element and the second terminal of the second NV memory element;
a first source line coupled to the second terminal of the first NV memory element;
a second source line coupled to the first terminal of the second NV memory element;
a second transistor having a first current electrode coupled to the complementary bit line, a control electrode coupled to the first word line, and a second current electrode coupled to the first terminal of the third NV memory element and the second terminal of the fourth NV memory element;
a third source line coupled to the second terminal of the third NV memory element; and
a fourth source line coupled to the first terminal of the fourth NV memory element.
2. The memory device of claim 1 , wherein the first transistor, the second transistor and the first, second, third, and fourth NV memory elements comprise a two bit NV memory unit.
3. The memory device of claim 1 , wherein:
the first and fourth NV memory elements comprise a first bit of the two bit memory unit and the second and third NV memory elements comprise a second bit of the two bit memory unit.
4. The memory device of claim 1 , wherein:
during a read of the first bit of the two bit memory unit, the first word line is for causing the first and second transistors to couple the first terminal of the first NV memory element to the true bit line and the second terminal of the fourth NV memory element to the complementary bit line and the first and fourth source lines are for providing a current sink.
5. The memory device of claim 1 , wherein:
during a write of a logic high to the first bit, the first word line is for causing the first and second transistors to simultaneously couple the first terminal of the first NV memory element to the true bit line and the second terminal of the fourth NV memory element to the complementary bit line, the first source line is for receiving a low potential, the true bit line is for receiving a write voltage, the complementary bit line is for receiving the low potential, and the fourth source line is for receiving the write voltage.
6. The memory device of claim 5 , wherein during the write of a logic high to the first bit, the second source line and the third source line are for receiving a reference voltage.
7. The memory device of claim 6 , wherein the reference voltage is between the low potential and the logic high.
8. The memory device of claim 7 , wherein the reference voltage is halfway between the low potential and the logic high.
9. The memory device of claim 1 , further comprising:
a second word line;
wherein the plurality of NV memory elements further comprises a fifth NV memory element, a sixth NV memory element, a seventh NV memory element, and an eighth NV memory element, wherein each of the fifth, sixth, seventh, and eighth NV memory elements are characterized as having a first terminal and second terminal, wherein the higher resistance state is established by providing the write current from the first terminal to the second terminal and the lower resistance state is established by providing the write current from the second terminal to the first terminal;
a third transistor having a first current electrode coupled to the true bit line, a control electrode coupled to the second word line, and a second current electrode coupled to the second terminal of the fifth NV memory element and the first terminal of the sixth NV memory element, wherein the third source line is coupled to the first terminal of the fifth NV memory element, and the fourth source line is coupled to the second terminal of the sixth NV memory element;
a fourth transistor having a first current electrode coupled to the complementary bit line, a control electrode coupled to the second word line, and a second current electrode coupled to the second terminal of the seventh NV memory element and the first terminal of the eighth NV memory element;
a fifth source line coupled to the first terminal of the seventh NV memory element; and
a sixth source line coupled to the second terminal of the eighth NV memory element.
10. The memory device of claim 1 , further comprising:
a second word line;
wherein the plurality of NV memory elements further comprises a fifth NV memory element, a sixth NV memory element, a seventh NV memory element, and an eighth NV memory element, wherein each of the fifth, sixth, seventh, and eighth NV memory elements are characterized as having a first terminal and second terminal, wherein the higher resistance state is established by providing the write current from the first terminal to the second terminal and the lower resistance state is established by providing the write current from the second terminal to the first terminal;
a third transistor having a first current electrode coupled to the true bit line, a control electrode coupled to the second word line, and a second current electrode coupled to the first terminal of the fifth NV memory element and the second terminal of the sixth NV memory element, wherein the first source line is coupled to the second terminal of the fifth NV memory element, and the second source line is coupled to the first terminal of the sixth NV memory element; and
a fourth transistor having a first current electrode coupled to the complementary bit line, a control electrode coupled to the second word line, and a second current electrode coupled to the first terminal of the seventh NV memory element and the second terminal of the eighth NV memory element, wherein the third source line is coupled to the first terminal of the seventh NV memory element and the fourth source line is coupled to the second terminal of the first terminal of the eighth NV memory element.
11. A method of operating a memory device in which the memory device comprises a first bit having a first portion in a first memory unit and a second portion in a second memory unit and a second bit having a first portion in the first memory unit and a second portion in the second memory unit, the first portions are complementary to the second portions, wherein the first unit is coupled to a word line, a true bit line, a first source line, and a second source line, the second unit is coupled to the word line, a complementary bit line, a third source line and a fourth source line, the first and second portions comprise non-volatile (NV) memory units which are written to a relatively high resistance with a write current passing from a first terminal to a second terminal and to a relatively low resistance with a write current passing from the second terminal to the first terminal, the method comprising:
writing a first state into the first bit by writing a relatively high resistance into the first portion of the first unit using the true bit line and a relatively low resistance into the first portion of the second unit using the complementary bit line; and
sensing a logic state of the first bit by coupling the first portion of the first unit to the true bit line and the first portion of the second unit to the complementary bit line by enabling the word line and using differential sensing on the true bit line and the complementary bit line.
12. The method of claim 11 , wherein the differential sensing comprises sensing a voltage differential between the true bit line and the complementary bit line.
13. The method of claim 11 , wherein the differential sensing comprises sensing a current differential between the true bit line and the complementary bit line.
14. The method of claim 11 , wherein the writing a relatively high resistance into the first portion of the first unit using the true bit line and a relatively low resistance into the first portion of the second unit is performed simultaneously.
15. The method of claim 11 , further comprising sensing a logic state of the second bit by coupling the second portion of the first unit to the true bit line and the second portion of the second unit to the complementary bit line by enabling the word line and using differential sensing on the true bit line and the complementary bit line.
16. The method of claim 15 , further comprising enabling the first and fourth source lines during the writing the first logic state into the first portions of the first and second units.
17. The method of claim 16 , wherein the enabling the first and fourth source lines comprises coupling the first and fourth source lines to ground.
18. The method of claim 11 , further comprising:
writing a second state into the first bit by writing a relatively high resistance into the second portion of the first unit using the true bit line and the second source line and a relatively low resistance into the second portion of the second unit using the complementary bit line and the third source line.
19. The method of claim 18 , wherein the writing the second state comprises flowing current from the second source to the true bit line through the second portion of the first unit and from the third source line to the complementary bit line through the second portion of the second unit.
20. A memory array, comprising:
a first bit line and a second bit line;
a first word line and a second word line;
a first source line, a second source line, a third source line, and a fourth source line;
a plurality of non-volatile (NV) memory elements each characterized as having a first terminal and second terminal, wherein a higher resistance state is established by providing a write current from the first terminal to the second terminal and a lower resistance state is established by providing a write current from the second terminal to the first terminal;
a first NV unit, comprising:
a first NV memory element and a second NV memory element of the plurality of NV memory elements; and
a first transistor having a control electrode coupled to the first word line, a first current electrode coupled to the first bit line, and a second current electrode coupled to the first terminal of the first NV memory element and the second terminal of the second NV memory element, wherein the first source line is coupled to the second terminal of the first NV memory element and the second source line is coupled to the first terminal of the second NV memory element;
a second NV unit, comprising:
a third NV memory element and a fourth NV memory element of the plurality of NV memory elements; and
a second transistor having a control electrode coupled to the first word line, a first current electrode coupled to the second bit line, and a second current electrode coupled to the first terminal of the third NV memory element and the second terminal of the fourth NV memory element, wherein the third source line is coupled to the second terminal of the third NV memory element and the fourth source line is coupled to the first terminal of the fourth NV memory element; and
a third NV unit, comprising:
a fifth NV memory element and a sixth NV memory element of the plurality of NV memory elements; and
a third transistor having a control electrode coupled to the second word line, a first current electrode coupled to the first bit line, and a second current electrode coupled to the second terminal of the fifth NV memory element and the first terminal of the fourth NV memory element, wherein the third source line is coupled to the first terminal of the fifth NV memory element and the fourth source line is coupled to the second terminal of the sixth NV memory element.