Passive tunable integrated circuit (PTIC) and related methods
A passive tunable integrated circuit (PTIC) includes a semiconductor die (die) having a plurality of barium strontium titanate (BST) tunable capacitors. The plurality of BST tunable capacitors collectively define a capacitative area of the die. At least one electrical contact is electrically coupled with the plurality of BST tunable capacitors. A redistribution layer electrically couples the at least one electrical contact with at least one electrically conductive contact pad (contact pad). The at least one contact pad is located over the capacitative area. A bump electrically couples with the at least one contact pad and is located over the capacitative area. An electrically insulative layer couples between each contact pad of the PTIC and the plurality of BST tunable capacitors.
1. A passive tunable integrated circuit (PTIC) comprising:
a semiconductor die (die) having a barium strontium titanate (BST) tunable capacitor;
an overlayer coupled over the BST tunable capacitor, and;
a redistribution layer electrically coupling at least one electrical contact of the BST tunable capacitor with at least one electrically conductive contact pad (contact pad);
wherein the overlayer comprises a plurality of holes therethrough, the plurality of holes arranged in a reticulation pattern, each hole extending through the overlayer from a top surface of the overlayer to a bottom surface of the overlayer, and;
wherein the plurality of holes are adapted to reduce stress of the overlayer through the reticulation pattern.
2. The PTIC of claim 1 , wherein the BST tunable capacitor defines a capacitative area of the die, wherein the at least one contact pad is electrically coupled with a bump, and wherein the bump is located at least partially over the capacitative area.
3. The PTIC of claim 2 , wherein each active bump of the PTIC is located substantially over the capacitative area.
4. The PTIC of claim 3 , wherein each active bump of the PTIC is located entirely over the capacitative area.
5. The PTIC of claim 1 , wherein the die is not packaged using a leadframe.
6. The PTIC of claim 1 , wherein an electrically insulative layer is coupled between each contact pad of the PTIC and the BST tunable capacitor.
7. The PTIC of claim 2 , wherein the at least one contact pad is located at least partially over the capacitative area.
8. The PTIC of claim 7 , wherein the at least one contact pad is located substantially over the capacitative area.
9. The PTIC of claim 8 , wherein the at least one contact pad is located entirely over the capacitative area.
10. The PTIC of claim 2 , wherein the bump is physically coupled with the BST tunable capacitor through an electrically insulative layer.