Test circuit for very low voltage and bias scan testing of integrated circuit
View Patent ↗Test circuitry for an integrated circuit (IC) that has a scan chain includes a control unit for applying a test pattern and a clock signal to the scan chain, and for varying the level of a supply voltage during a scan test procedure. In a first test phase, the supply voltage is set to the rated voltage level of the IC while a test pattern is shifted into the scan chain at a fast rate. A second, capture phase is run at a lower rate and the supply voltage is reduced to a lower level such that defects that cannot be detected when the capture phase is run at the rated voltage are observable yet switching elements in the IC still function correctly. Running the shift phase at the higher speed reduces the overall test time compared with known very low voltage (VLV) scan test procedures.
1. Test circuitry for an integrated circuit (IC) device having at least one scan chain, the test circuitry comprising:
a control unit operably coupled to the at least one scan chain for applying a test pattern and a clock signal to the at least one scan chain; and
a voltage supply module operably coupled to the control unit and the IC device for applying an operating voltage to the IC device based on a supply voltage and a ground reference provided by the voltage supply module,
wherein the control unit sets, in a scan shift phase, the operating voltage of the IC device to a first voltage level and a frequency of the clock signal to a first frequency value, and in a scan capture phase, the control unit sets the operating voltage of the IC device to a second voltage level that is less than the first voltage level by positively biasing the ground reference of the voltage supply module, and the frequency of the clock signal to a second frequency value, such that the IC device is powered at the second voltage level in the scan capture phase.
2. The test circuitry of claim 1 , wherein the second voltage level is lower than the first voltage level and the second clock frequency value is lower than the first clock frequency value.
3. The test circuitry of claim 1 , wherein the second voltage level is higher than the first voltage level.
4. The test circuitry of claim 3 , wherein the control unit controls the voltage supply module to set the first voltage level to a voltage level equal to a rated voltage of the IC device.
5. The test circuitry of claim 3 , wherein the control unit controls the voltage supply module to set the second voltage level to a voltage level equal to a rated voltage of the IC device.
6. A method for testing an integrated circuit (IC) comprising at least one scan chain for receiving a test pattern and a clock signal, the method comprising:
in a scan shift phase, setting an operating voltage of the IC to a first voltage level by providing a supply voltage and a ground reference to the IC and a frequency of the clock signal to a first frequency value; and
in a scan capture phase, setting the operating voltage of the IC to a second voltage level that is different from the first voltage level by biasing the ground reference, and the frequency of the clock signal to a second frequency value, such that the IC is powered at the second voltage level in the scan capture phase.
7. The method of claim 6 , further comprising setting the second voltage level to a level that is lower than the first voltage level and setting the second clock frequency value to a value that is lower than the first clock frequency value.
8. The method of claim 7 , further comprising setting the first voltage level to a level equal to a rated voltage of the IC.
9. The method of claim 6 , further comprising setting the second voltage level to a level that is higher than the first voltage level.
10. The method of claim 9 , further comprising setting the second voltage level to a level equal to a rated voltage of the IC.
11. The method of claim 9 , further comprising determining a value for the first voltage level by running multiple scan chain tests at different voltages until no scan shift failures are detected.
12. The method of claim 6 , further comprising:
in a first scan shift phase, shifting a first test pattern into the scan chain, and
in a second scan shift phase following the scan capture phase, shifting a response to the first test pattern out of the scan chain,
wherein during both the first and second scan shift phases, the operating voltage of the IC is set to the first voltage level and the frequency of the clock signal is set to the first frequency value.
13. The method of claim 12 , wherein during the second scan shift phase, a second test pattern is scanned into the scan chain.
14. An integrated circuit (IC) device, comprising:
at least one scan chain;
a test control unit operably coupled to the scan chain for applying a test pattern and a clock signal to the scan chain; and
a voltage supply module operably coupled to the test control unit for applying an operating voltage to the scan chain based on a supply voltage and a ground reference provided by the voltage supply module,
wherein the test control unit is arranged to set, in a scan shift phase, the operating voltage of the IC device to a first voltage level and a frequency of the clock signal to a first frequency value, and in a scan capture phase, to set the operating voltage of the IC device to a second voltage level that is different from the first voltage level by biasing the round reference of the voltage supply module, and the frequency of the clock signal to a second frequency value, such that the IC device is powered at the second voltage level in the scan capture phase.
15. The test circuitry of claim 1 , wherein the voltage supply module comprises a digital-to-analog converter and a voltage regulator coupled to the digital-to-analog converter, wherein the control unit sets the operating voltage by controlling at least one of the digital-to-analog converter and the voltage regulator.
16. The test circuitry of claim 15 , wherein the control unit sets the operating voltage by controlling the digital-to-analog converter.