Granted Patent B1

US 9,508,632 · App. 14/749,243 · Granted Nov 29, 2016

Abstract

Claims (37)

1. A semiconductor structure comprising:

a lead frame having a flag and a plurality of leads, the plurality of leads having a first pitch;

a semiconductor die attached to a first major surface of the flag; and

a plurality of re-routed lead fingers attached to the lead frame, wherein:

a first end of each re-routed lead finger of the plurality of re-routed lead fingers is attached to a lead of the plurality of leads,

each re-routed lead finger extends over the semiconductor die such that a second end of each re-routed lead finger is over and spaced apart from the flag of the lead frame, and

the second ends of the plurality of re-routed lead fingers has a second pitch different from the first pitch;

a mold compound around the semiconductor die and between the second ends of the plurality of re-routed lead fingers and a top surface of the semiconductor die; and

a plurality of wirebond connections between the top surface of the semiconductor die and the plurality of leads of the lead frame, wherein the plurality of re-routed lead fingers extend over the plurality of wirebond connections.

2. The semiconductor structure of claim 1 , further comprising:

a packaged semiconductor device in electrical contact with the second ends of the plurality of re-routed lead fingers.

3. The semiconductor structure of claim 2 , wherein the packaged semiconductor device is characterized as one of a wafer level chip scale package, land grid array package, or a micro-electromechanical semiconductor (MEMs) package.

4. The semiconductor structure of claim 1 , wherein each re-routed lead finger extends from a corresponding lead at an angle less than 90 degrees.

5. The semiconductor structure of claim 1 , wherein a top surface of the mold compound exposes a portion, including the second end, of each of the plurality of re-routed lead fingers, wherein at least one exposed portion includes a bend at the top surface of the mold compound.

6. The semiconductor structure of claim 1 , wherein the plurality of re-routed lead fingers has fewer re-routed lead fingers than the plurality of leads has leads.

7. A semiconductor structure comprising:

a lead frame having a flag and a plurality of leads;

a semiconductor die attached to a first major surface of the flag;

a plurality of re-routed lead fingers attached to the lead frame, wherein:

a first end of each re-routed lead finger of the plurality of re-routed lead fingers is attached to a lead of the plurality of leads, wherein at least one lead of the plurality of leads does not have an attached re-routed lead finger, and

each re-routed lead finger extends over the semiconductor die such that a second end of each re-routed lead finger is over and spaced apart from a top surface of the semiconductor die; and

a mold compound around the semiconductor die and between the plurality of re-routed lead fingers and the top surface of the semiconductor die which exposes a portion, including the second end, of each re-routed lead finger; and

a packaged semiconductor device over the semiconductor die and in electrical contact with the exposed second ends of the plurality of re-routed lead fingers.

8. The semiconductor structure of claim 7 , further comprising:

a plurality of wirebond connections between the top surface of the semiconductor die and the plurality of leads of the lead frame.

9. The semiconductor structure of claim 8 , wherein the plurality of re-routed lead fingers extend over the plurality of wirebond connections.

10. The semiconductor structure of claim 9 , wherein each re-routed lead finger extends from an attached lead at an angle of 90 degrees or less.

11. The semiconductor structure of claim 7 , wherein an exposed portion of at least one of the plurality of re-routed lead fingers includes a bend in a plane parallel to the top surface of the semiconductor die.

12. The semiconductor structure of claim 7 , wherein the plurality of leads has a first pitch and the second ends of the plurality of re-routed lead fingers has a second pitch different from the first pitch.

13. The semiconductor structure of claim 7 , wherein the exposed portions of at least two of the plurality of re-routed lead fingers have a different length or width.

14. The semiconductor structure of claim 7 , wherein the plurality of re-routed lead fingers is a preformed structure.

15. A method for forming a stacked semiconductor device, comprising:

attaching a semiconductor die to a flag of a lead frame, wherein the lead frame has a plurality of leads having a first pitch;

attaching a first end of each of a plurality of re-routed lead fingers to a lead of the plurality of leads, wherein each re-routed lead finger extends over the semiconductor die such that a second end of each re-routed lead finger is over and spaced apart from the flag of the lead frame, and wherein the second ends of the plurality of re-routed lead fingers has a second pitch different from the first pitch, wherein the plurality of re-routed lead fingers has fewer re-routed lead fingers than the plurality of leads has leads; and

attaching a packaged semiconductor device to be in electrical contact with the second ends of the plurality of re-routed lead fingers.

16. The method of claim 15 , further comprising:

prior to attaching the packaged semiconductor device, forming a mold compound around the semiconductor die and between the second ends of the plurality of re-routed lead fingers and a top surface of the semiconductor die, wherein the mold compound exposes a portion, including the second end, of each re-routed lead finger, and wherein the packaged semiconductor device is in electrical contact with the exposed portions of the re-routed lead fingers.

Assignments (9)