Systems and methods for asymmetric memory access to memory banks within integrated circuit systems
Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.
1. A system for asymmetric memory access in an integrated circuit, comprising:
a memory including a plurality of memory banks; and
a memory controller including a plurality of access ports coupled to the memory banks, the memory controller being configured to provide asymmetric memory access for access requests to the memory banks based upon an access port and a memory bank to be used for each memory access request;
wherein, for each access port, the memory controller is further configured to provide the asymmetric memory access by selecting a memory access time from at least two different memory access times based upon the memory bank to be accessed for each access request;
wherein the memory and the memory controller are within a single integrated circuit; and
wherein the different memory access times for each access port are based upon physical separation between the access port and the memory banks on the single integrated circuit.
2. The system of claim 1 , wherein the memory controller is further configured to receive parallel memory access requests from a plurality of bus masters, and wherein each bus master is associated with one of the access ports.
3. The system of claim 1 , wherein each access port uses an intervening register to access at least one of the memory banks and also uses no intervening register to access at least one of the memory banks.
4. The system of claim 1 , wherein the different access times comprise a plurality of sets of access times, each set being associated with one of the access ports.
5. The system of claim 4 , wherein each set of access times comprises a separate access time for each memory bank within the memory.
6. The system of claim 1 , wherein the different access times comprise different numbers of clock cycles for memory operations.
7. The system of claim 1 , wherein the memory controller is configured to translate logical memory addresses within access requests to physical memory addresses associated with the memory banks.
8. The system of claim 1 , wherein, for each access port, the memory controller is configured to use at least two different memory access bandwidths for connections between the access port and the memory banks to provide the asymmetric memory access based upon the memory bank to be accessed for each access request.
9. The system of claim 8 , wherein the different memory access bandwidths comprise different clock frequencies for clock signals associated with the connections between each access port and the memory banks.
10. The system of claim 8 , wherein the memory access bandwidths comprise at least one of different data path sizes for the connections between each access port and the memory banks or at least one shared data path between each access port and the memory banks.
11. A method for asymmetric memory access in an integrated circuit, comprising:
receiving memory access requests with a memory controller to access a memory having a plurality of memory banks, the memory controller having a plurality of access ports coupled to the memory, and the memory controller and the memory being within a single integrated circuit;
determining, with the memory controller, memory banks to access for the memory access requests; and
asymmetrically accessing, with the memory controller, the memory banks for the memory access requests based upon an access port and a memory bank to be used for each memory access request;
wherein, for each access port, the memory controller provides the asymmetric memory access by selecting a memory access time from at least two different memory access times based upon the memory bank to be accessed for each access request; and
wherein the different memory access times for each access port are based upon physical separation between the access port and the memory banks on the single integrated circuit.
12. The method of claim 11 , further comprising receiving parallel memory access requests from a plurality of bus masters, each bus master being associated with one of the access ports.
13. The method of claim 11 , wherein each access port uses an intervening register to access at least one of the memory banks and also uses no intervening register to access at least one of the memory banks.
14. The method of claim 11 , wherein the different access times comprise a plurality of sets of access times, each set being associated with one of the access ports.
15. The method of claim 14 , wherein each set of access times comprises a separate access time for each memory bank within the memory.
16. The method of claim 13 , wherein the different access times comprise different numbers of clock cycles for memory operations.
17. The method of claim 11 , further comprising translating logical memory addresses within access requests to physical memory addresses associated with the memory banks.
18. The method of claim 11 , further comprising, for each access port, communicating between the access port and the memory banks using a plurality of memory access bandwidths to provide the asymmetric accessing based upon the memory bank to be accessed for each access request.
19. The method of claim 18 , wherein the different memory access bandwidths comprise different clock frequencies for clock signals associated with the communications between each access port and the memory banks.
20. The method of claim 18 , wherein the memory access bandwidths comprise at least one of different data path sizes for the communications between each access port and the memory banks or at least one shared data path between each access port and the memory banks.