Integrated circuit structure with methods of electrically connecting same
Embodiments of the present disclosure provide an integrated circuit (IC) structure and methods of electrically connecting multiple IC structures. An IC structure according to embodiments of the present disclosure can include: a first conductive region; a second conductive region laterally separated from the first conductive region; a first vertically-oriented semiconductor fin formed over and contacting the first conductive region; a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes: a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and a substantially vertical section contacting the second conductive region.
1. An integrated circuit (IC) structure comprising:
a first conductive region;
a second conductive region laterally separated from the first conductive region;
a first vertically-oriented semiconductor fin formed over and contacting the first conductive region;
a second vertically-oriented semiconductor fin formed over and contacting the second conductive region;
a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes:
a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and
a substantially vertical section contacting the second conductive region; and
a second gate contacting each of the second vertically-oriented semiconductor fin and the first conductive region, wherein the second gate includes:
a substantially horizontal section contacting the second vertically-oriented semiconductor fin, and
a substantially vertical section contacting the first conductive region.
2. The IC structure of claim 1 , further comprising:
a third vertically-oriented semiconductor fin formed over and contacting the first conductive region, and electrically connected to the first gate;
a fourth vertically-oriented semiconductor fin formed over and contacting the first conductive region;
a fifth vertically-oriented semiconductor fin formed over and contacting the second conductive region, and electrically connected to the second gate; and
a sixth vertically-oriented semiconductor fin formed over and contacting the second conductive region, wherein the first, second, third, fourth, fifth, and sixth vertically-oriented semiconductor fins comprise portions of respective FinFET transistors of a static random access memory (SRAM) cell.
3. The IC structure of claim 1 , wherein a vertical length to horizontal length aspect ratio of one of the first semiconductor fin and the second semiconductor fin is at least approximately two-to-one.
4. The IC structure of claim 1 , wherein a perimeter edge of the first vertically-oriented semiconductor fin is substantially vertically aligned with a perimeter edge of the first conductive region, and wherein a perimeter edge of the second vertically-oriented semiconductor fin is substantially vertically aligned with a perimeter edge of the second conductive region.
5. The IC structure of claim 1 , wherein the first gate substantially wraps around at least one of the first semiconductor fin and the second semiconductor fin.
6. The IC structure of claim 1 , wherein at least one of the first conductive region and the second conductive region comprises one of a p-doped semiconductor region, an n-doped semiconductor region, and a silicide region.
7. The IC structure of claim 1 , wherein the first conductive region and the second conductive region each comprise a doped semiconductor layer of a silicon-on-insulator (SOI) structure.
8. An integrated circuit (IC) structure comprising:
a first conductive region;
a second conductive region laterally separated from the first conductive region;
a first vertically-oriented semiconductor fin formed over and contacting the first conductive region;
a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and
a first gate contacting the first vertically-oriented semiconductor fin; and
a first contact positioned over the second conductive region and extending vertically through the first gate, wherein the first contact electrically connects the first gate to the second conductive region.
9. The IC structure of claim 8 , further comprising:
a second gate contacting the second vertically-oriented semiconductor fin; and
a second contact positioned over the first conductive region and extending vertically through each of the insulator and the first gate, wherein the first contact electrically connects the second gate to the first conductive region.
10. The IC structure of claim 9 , further comprising:
a third vertically-oriented semiconductor fin formed over and contacting the first conductive region, and electrically connected to the first gate;
a fourth vertically-oriented semiconductor fin formed over and contacting the first conductive region;
a fifth vertically-oriented semiconductor fin formed over and contacting the second conductive region, and electrically connected to the second gate; and
a sixth vertically-oriented semiconductor fin formed over and contacting the second conductive region, wherein the first, second, third, fourth, fifth, and sixth vertically-oriented semiconductor fins comprise portions of respective FinFET transistors of a static random access memory (SRAM) cell.
11. The IC structure of claim 8 , wherein a vertical length to horizontal length aspect ratio of one of the first semiconductor fin and the second semiconductor fin is at least approximately two-to-one.
12. The IC structure of claim 8 , wherein a perimeter edge of the first vertically-oriented semiconductor fin is substantially vertically aligned with a perimeter edge of the first conductive region, and wherein a perimeter edge of the second vertically-oriented semiconductor fin is substantially vertically aligned with a perimeter edge of the second conductive region.
13. The IC structure of claim 8 , wherein the first gate substantially wraps around at least one of the first semiconductor fin and the second semiconductor fin.
14. The IC structure of claim 8 , wherein at least one of the first conductive region and the second conductive region comprises one of a p-doped semiconductor region, an n-doped semiconductor region, and a silicide region.
15. The IC structure of claim 8 , wherein the first conductive region and the second conductive region each comprise a doped semiconductor layer of a silicon-on-insulator (SOI) structure.
16. An integrated circuit (IC) structure comprising:
a first conductive region;
a second conductive region laterally separated from the first conductive region;
a first vertically-oriented semiconductor fin formed over and contacting the first conductive region;
a second vertically-oriented semiconductor fin formed over and contacting the second conductive region, wherein a vertical length to horizontal length aspect ratio of one of the first vertically-oriented semiconductor fin and the second vertically-oriented semiconductor fin is at least approximately two-to-one; and
a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes:
a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and
a substantially vertical section contacting the second conductive region.
17. The IC structure of claim 16 , further comprising a second gate contacting each of the second vertically-oriented semiconductor fin and the first conductive region, wherein the second gate includes:
a substantially horizontal section contacting the second vertically-oriented semiconductor fin, and
a substantially vertical section contacting the first conductive region.
18. The IC structure of claim 16 , wherein a perimeter edge of the first vertically-oriented semiconductor fin is substantially vertically aligned with a perimeter edge of the first conductive region, and wherein a perimeter edge of the second vertically-oriented semiconductor fin is substantially vertically aligned with a perimeter edge of the second conductive region.
19. The IC structure of claim 16 , wherein the first gate substantially wraps around at least one of the first semiconductor fin and the second semiconductor fin.