Vertical bit line wide band gap TFT decoder
A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a body formed from a wide energy band gap semiconductor is disclosed. The wide energy band gap semiconductor may be an oxide semiconductor, such as a metal oxide semiconductor. As examples, this could be an InGaZnO, InZnO, HfInZnO, or ZnInSnO body. The source and drains can also be formed from the wide energy band gap semiconductor, although these may be doped for better conduction. The vertically oriented TFT selection device serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device has a high drive current, a high breakdown voltage and low leakage current.
1. A method for forming a non-volatile storage system, the method comprising:
forming a three dimensional memory array of memory cells above a substrate;
forming a plurality of word lines coupled to a subset of the memory cells;
forming a plurality of global bit lines;
forming a plurality of vertically oriented bit lines coupled to the memory cells, wherein the vertically oriented bit lines are oriented vertically with respect to the substrate; and
forming a plurality of vertically oriented thin film transistor (TFT) select devices, wherein the vertically oriented TFT select devices are oriented vertically with respect to the substrate;
wherein forming each of the vertically oriented TFT select devices comprises:
forming a first source/drain electrically coupled to a first global bit line of the global bit lines;
forming a body that includes a wide band gap semiconductor having an energy band gap greater than 1.1 eV;
forming a second source/drain electrically coupled to a first vertically oriented bit line of the vertically oriented bit lines;
forming a gate; and
forming a gate dielectric between the gate and the body;
forming a plurality of select lines, wherein each of the select lines is coupled to the gates of a group of the plurality of vertically oriented TFT select devices; and
forming a plurality of select line drivers associated with the plurality of select lines, each of the select line drivers configured to apply a signal to its associated select line to cause a given vertically oriented TFT select device to connect or disconnect its associated vertically oriented bit line to or from its associated global bit line.
2. The method of claim 1 , wherein the forming the body that includes the wide band gap semiconductor comprises forming a region of oxide semiconductor.
3. The method of claim 1 , wherein the forming the body that includes the wide band gap semiconductor comprises forming the body from a metal oxide semiconductor.
4. The method of claim 1 , wherein the forming the body that includes the wide band gap semiconductor comprises forming the body from a material that includes indium.
5. The method of claim 1 , wherein forming the first source/drain and forming the second source/drain comprises:
doping the wide band gap semiconductor either N+ or P+ to form the first source/drain and doping the wide band gap semiconductor either N+ or P+ to form the second source/drain to have the same conductivity as the first source/drain, the body having a lower impurity concentration than the first and second source/drains.
6. The method of claim 1 , wherein forming the wide band gap semiconductor comprises:
forming the body without providing an impurity to dope the wide band gap semiconductor, wherein the body is intrinsic.
7. The method of claim 1 , wherein forming the first source/drain and forming the second source/drain comprises:
forming a first metal region directly connected to the wide band gap semiconductor that forms the body; and
forming a second metal region directly connected to the wide band gap semiconductor that forms the body.
8. The method of claim 7 , wherein forming the vertically oriented TFT select device further comprises:
forming the body and the gate such that the body extends past the gate to form a channel extension where the gate is not adjacent to the body.
9. A method for forming a non-volatile storage system, the method comprising:
forming a three dimensional memory array of ReRAM memory cells above a substrate;
forming a plurality of word lines coupled to a subset of the ReRAM memory cells;
forming a plurality of global bit lines;
forming a plurality of vertically oriented bit lines coupled to the memory cells, wherein the vertically oriented bit lines are oriented vertically with respect to the substrate; and
forming a plurality of vertically oriented thin film transistor (TFT) select devices, wherein the vertically oriented TFT select devices are oriented vertically with respect to the substrate;
wherein forming each of the vertically oriented TFT select devices comprises:
forming a first source/drain that is an oxide semiconductor and that is electrically coupled to a first global bit line of the global bit lines;
forming a body that is the oxide semiconductor;
forming a second source/drain that is the oxide semiconductor and is electrically coupled to a first vertically oriented bit line of the vertically oriented bit lines;
forming a gate; and
forming a gate dielectric between the gate and the body;
forming a plurality of select lines, wherein each of the select lines is coupled to the gates of a group of the plurality of vertically oriented TFT select devices; and
forming a plurality of select line drivers associated with the plurality of select lines, each of the select line drivers configured to apply a signal to its associated select line to cause a given vertically oriented TFT select device to connect or disconnect its associated vertically oriented bit line to or from its associated global bit line.
10. The method of claim 9 , wherein the forming the body that is the oxide semiconductor comprises forming the body from a wide band gap semiconductor having an energy band gap greater than 1.1 eV.
11. The method of claim 9 , wherein the forming the body that is the oxide semiconductor comprises forming the body from a metal oxide semiconductor.
12. The method of claim 9 , wherein the forming the body that is the oxide semiconductor comprises forming the body from a material that includes indium.
13. The method of claim 9 , wherein forming the first source/drain and forming the second source/drain comprises:
doping the oxide semiconductor either N+ or P+ to form the first source/drain and doping the oxide semiconductor either N+ or P+ to form the second source/drain to have the same conductivity as the first source/drain, the body having a lower impurity concentration than the first and second source/drains.
14. The method of claim 13 , wherein forming the vertically oriented TFT select device further comprises:
forming the body and the gate such that the body extends past the gate to form a channel extension where the gate is not adjacent to the body.
15. A method for forming a non-volatile storage system, the method comprising:
forming a three dimensional memory array of ReRAM memory cells above a substrate;
forming a plurality of word lines coupled to a subset of the ReRAM memory cells;
forming a plurality of global bit lines;
forming a plurality of vertically oriented bit lines coupled to the memory cells, wherein the vertically oriented bit lines are oriented vertically with respect to the substrate; and
forming a plurality of vertically oriented thin film transistor (TFT) select devices, wherein the vertically oriented TFT select devices are oriented vertically with respect to the substrate;
wherein forming each of the vertically oriented TFT select devices comprises:
forming a first source/drain that is a metal and that is electrically coupled to a first global bit line of the global bit lines;
forming a body that is an oxide semiconductor that is in direct contact with the metal of the first source/drain;
forming a second source/drain that is a metal that is in direct contact with the oxide semiconductor of the body and is electrically coupled to a first vertically oriented bit line of the vertically oriented bit lines;
forming a gate; and
forming a gate dielectric between the gate and the body;
forming a plurality of select lines, wherein each of the select lines is coupled to the gates of a group of the plurality of vertically oriented TFT select devices; and
forming a plurality of select line drivers associated with the plurality of select lines, each of the select line drivers configured to apply a signal to its associated select line to cause a given vertically oriented TFT select device to connect or disconnect its associated vertically oriented bit line to or from its associated global bit line.
16. The method of claim 15 , wherein the forming the body that is the oxide semiconductor comprises forming the body from a wide band gap semiconductor having an energy band gap greater than 1.1 eV.
17. The method of claim 15 , wherein the forming the body that is the oxide semiconductor comprises forming the body from a metal oxide semiconductor.
18. The method of claim 15 , wherein the forming the body that is the oxide semiconductor comprises forming the body from a material that includes indium.
19. The method of claim 15 , wherein the three dimensional memory array is a monolithic three dimensional memory array comprising multiple memory levels above the substrate.
20. The method of claim 5 , wherein forming the vertically oriented TFT select device further comprises:
forming the body and the gate such that the body extends past the gate to form a channel extension where the gate is not adjacent to the body.