Method of fabricating integrated circuit (IC) devices

1. A method of fabricating integrated circuit (IC) devices, comprising:

forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends;

forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends;

forming top interconnecting elements on the lower surface of the top substrate around the top inductor area, wherein the top interconnecting elements are formed concurrently with the top inductor structure;

forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area, wherein the bottom interconnecting elements are formed concurrently with the bottom inductor structure;

forming a mask over each of the top and bottom inductor structures;

forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements;

removing the mask; and

connecting the top and bottom interconnecting elements to each other.

2. The method according to claim 1 , wherein forming each of the top and bottom inductor structures comprises:

forming a coil of conductive material, the coil having first and second terminals at its opposite ends.

3. The method according to claim 1 , further comprising:

forming the top interconnecting elements, the bottom interconnecting elements, and solder bumps and forming a mask over the solder bumps prior to forming the top and bottom inductor structures; and

removing the mask subsequent to forming the top and bottom inductor structures.

4. The method according to claim 1 , further comprising:

forming a top barrier structure, in the top inductor area at the lower surface, spaced from and surrounding a perimeter of the top inductor structure;

forming a bottom barrier structure, in the bottom inductor area at the upper surface, spaced from and surrounding a perimeter of the bottom inductor structure;

depositing a layer of non-conductive bonding material, with a same thickness as the solder bumps, on lower and upper surfaces, respectively, of the top and bottom barrier structures; and

connecting the top and bottom barrier structures.

5. The method according to claim 4 , wherein the top and bottom inductor structures are separated from each other by an air gap.

6. The method according to claim 4 , wherein the top inductor structures, the top inductor areas, and top barrier structures are substantially a same geometrical shape as and are vertically aligned with the bottom inductor structures, bottom inductor areas, and bottom barrier structures, respectively.

7. The method according to claim 4 , further comprising:

injecting an under-fill material around the top and bottom barrier structures subsequent to connecting the top and bottom barrier structures.

8. The method according to claim 1 , wherein the top and bottom inductor structures are at a same height as the top and bottom interconnecting elements.

9. A method of fabricating integrated circuit (IC) devices, comprising:

forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends;

forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends,

wherein the top and bottom inductor structures include a coil of conductive material, the coil having first and second terminals at its opposite ends;

forming top interconnecting elements on the lower surface of the top substrate around the top inductor area;

forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area;

forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and

connecting the top and bottom interconnecting elements to each other,

wherein the method of fabricating IC devices further comprises:

forming a top barrier structure, in the top inductor area at the lower surface, spaced from and surrounding a perimeter of the top inductor structure;

forming a bottom barrier structure, in the bottom inductor area at the upper surface, spaced from and surrounding a perimeter of the bottom inductor structure,

wherein the top inductor structures, the top inductor areas, and top barrier structures are substantially a same geometrical shape as and are vertically aligned with the bottom inductor structures, bottom inductor areas, and bottom barrier structures, respectively, and wherein the top and bottom inductor structures are separated from each other by an air gap;

depositing a layer of non-conductive bonding material, with a same thickness as the solder bumps, on lower and upper surfaces, respectively, of the top and bottom barrier structures; and

connecting the top and bottom barrier structures.

10. The method according to claim 9 , further comprising:

injecting an under-fill material around the top and bottom barrier structures subsequent to connecting the top and bottom barrier structures.

11. The method according to claim 9 , wherein the top and bottom inductor structures are at a same height as the top and bottom interconnecting elements.