Integrated FinFET structure having a contact plug pitch larger than fin and first metal pitch
An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.
1. An integrated circuit (IC) structure comprising:
a semiconductor substrate;
at least a non-planar field effect transistor (FET) device formed on the semiconductor substrate, the non-planar FET device comprising a plurality of fins and a gate electrode, and the fins comprising a fin pitch;
an interconnection structure formed on the semiconductor substrate, the interconnection structure comprising a plurality of first group metals and a plurality of second group metals, the first group metals being formed on the non-planar FET device and the second group metals being formed on the first group metals, the first group metals comprising a first metal pitch, the second group metals comprising a second metal pitch, and the second metal pitch being 1.2-1.5 times the first metal pitch; and
a plurality of contact plugs formed on the non-planar FET device, the contact plugs physically contacting the gate electrode of the non-planar FET device and only one of the fins of the non-planar FET device, the contact plugs comprising a contact pitch, and the contact pitch being larger than the fin pitch and larger than the first metal pitch.
2. The integrated circuit structure according to claim 1 , wherein the contact plugs electrically connect the non-planar FET device and the first group metals of the interconnection structure.
3. The integrated circuit structure according to claim 1 , wherein the first group metals comprise no more than two layers.
4. The integrated circuit structure according to claim 1 , wherein the second group metals comprise no more than four layers.
5. The integrated circuit structure according to claim 4 , wherein each layer of the second group metals comprises metal structures and via structures.
6. The integrated circuit structure according to claim 1 , wherein the first metal pitch is smaller than a predetermined value.
7. The integrated circuit structure according to claim 6 , wherein the predetermined value is 75 nanometers (nm).
8. The integrated circuit structure according to claim 7 , wherein the second metal pitch is between 75 nm and 85 nm.
9. The integrated circuit structure according to claim 1 , further comprising a plurality of third group metals, and the third group metals comprise a third metal pitch.
10. The integrated circuit structure according to claim 9 , wherein the first metal pitch is smaller than a first predetermined value, the second metal pitch is larger than the first predetermined value and smaller than a second predetermined value, and the third metal pitch is larger than the second predetermined value.
11. The integrated circuit structure according to claim 10 , wherein the first predetermined value is 50 nm and the second predetermined value is 75 nm.
12. The integrated circuit structure according to claim 1 , wherein the fins of the non-planar FET device comprise silicon, germanium, or III-V semiconductor material.
13. The integrated circuit structure according to claim 1 , wherein the gate electrode of the non-planar FET device comprises a single work function metal layer or a multiple work function metal layer.