Double stepped semiconductor substrate

1. A device comprising:

a group IV semiconductor material layer having a double stepped surface, wherein a first component of the group IV semiconductor material is double bonded to a second component of the group IV semiconductor material; and

a group III-V semiconductor material layer disposed directly on the double stepped surface, wherein the group III-V semiconductor material layer includes a group III semiconductor material and a group V semiconductor, wherein the group III semiconductor material is doubled bonded to the group V semiconductor material, wherein the double stepped surface is free of the group IV semiconductor material being double bonded to the group V semiconductor material.

2. The device of claim 1 , wherein the group IV semiconductor material includes Si.

3. The device of claim 1 , wherein the first component of the group IV semiconductor material includes Si, and

wherein the second component of the group IV semiconductor material includes Si.

4. The device of claim 1 , wherein the group III semiconductor material includes Ga and the group V semiconductor material includes As.

5. The device of claim 1 , wherein the double stepped surface is positioned within an off-cut region of the group IV semiconductor material layer.

6. The device of claim 1 , wherein the double stepped surface does not cover the entire group IV semiconductor material layer.

7. The device of claim 1 , wherein the double stepped surface is free of anti-phase boundary (APB) defects.

8. A semiconductor substrate comprising:

an off-cut region formed through an etching process used in a Metal-Organic Chemical Vapor Deposition (MOCVD) process; and

a double stepped surface formed within the off-cut region, the double stepped surface being formed through an annealing process used in the MOCVD process and in the same chamber as the MOCVD process.

9. The semiconductor substrate of claim 8 , further comprising a group III-V semiconductor material layer disposed directly on the double stepped surface, wherein the group III-V semiconductor material layer includes a group III semiconductor material and a group V semiconductor, and

wherein the semiconductor substrate includes a group IV semiconductor material layer, and

wherein a first component of the group IV semiconductor material is double bonded to a second component of the group IV semiconductor material, and

wherein the group III semiconductor material is doubled bonded to the group V semiconductor material, wherein the double stepped surface is free of the group IV semiconductor material being double bonded to the group V semiconductor material.

10. The semiconductor substrate of claim 9 , wherein the first component of the group IV semiconductor material includes Si, and

wherein the second component of the group IV semiconductor material includes Si.

11. The semiconductor substrate of claim 10 , wherein the group III semiconductor material includes Ga and the group V semiconductor material includes As.

12. The semiconductor substrate of claim 9 , wherein the double stepped surface does not extend across the entire group IV semiconductor material layer.

13. The semiconductor substrate of claim 9 , wherein the group III-V semiconductor material only covers a portion of the group IV semiconductor material layer.

14. The semiconductor substrate of claim 8 , wherein the double stepped surface is free of anti-phase boundary (APB) defects.

15. A method for forming a double step surface on a semiconductor substrate, the method comprising:

with a Hydrogen Chloride (HCl) etching process used in situ with a Metal-Organic Chemical Vapor Deposition (MOCVD) process, forming an off-cut surface on a region of a semiconductor substrate;

with an annealing process used in situ with the MOCVD process, forming double stepped surface on the region of the semiconductor substrate; and

forming a III-V semiconductor layer onto the double stepped region with the MOCVD process;

wherein the double stepped region is such that there are fewer anti-phase boundary (APB) defects formed into the III-V semiconductor layer.

16. The method of claim 15 , wherein the semiconductor substrate is a IV semiconductor.

17. The method of claim 15 , wherein the double stepped surface is formed on-axis.

18. The method of claim 15 , wherein the formation of the double stepped surface is performed in the same chamber as an MOCVD process.

19. The method of claim 15 , wherein the formation of the double stepped surface is in situ with an MOCVD process.

20. The method of claim 15 , wherein the annealing process occurs at a temperature of about 1200° C.