IP Library Granted Patent US 9,397,230
Granted Patent B2
US 9,397,230 · App. 14/810,140 · Granted Jul 19, 2016

Zener diode devices and related fabrication methods

Inventors: Weize Chen (Phoenix, AZ); Xin Lin (Phoenix, AZ); Patrice M. Parris (Phoenix, AZ)
Assignee: Freescale Semiconductor, Inc.
H01L29/866H01L29/0611H01L29/0653H01L29/0688H01L29/0692H01L29/08H01L29/66106
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Quick Facts
Patent No.
US 9,397,230
App. No.
14/810,140
Granted
Jul 19, 2016
Kind
B2
Abstract

Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different.

Claims (40)

1. A diode comprising:

a first region having a first conductivity type;

a second region having a second conductivity type, the first region overlying the second region and the second region being adjacent to the first region to provide a vertical junction between the first region and the second region; and

a third region adjacent to the first region and the second region to provide a lateral junction between the third region and one of the first region or the second region, wherein:

the lateral junction influences a first reverse breakdown voltage of the vertical junction; and

a second reverse breakdown voltage of the lateral junction is greater than the first reverse breakdown voltage of the vertical junction.

2. The diode of claim 1 , wherein the lateral junction is angled with respect to the vertical junction.

3. The diode of claim 2 , wherein the lateral junction is substantially orthogonal to the vertical junction.

4. The diode of claim 1 , wherein the third region has the second conductivity type to provide the lateral junction between the third region and the first region.

5. The diode of claim 4 , wherein a dopant concentration of the third region is less than a second dopant concentration of the second region.

6. The diode of claim 4 , wherein a second dopant concentration of the second region is greater than a first dopant concentration of the first region.

7. The diode of claim 1 , wherein the third region has the first conductivity type to provide the lateral junction between the third region and the second region.

8. The diode of claim 7 , wherein a first dopant concentration of the first region is greater than a second dopant concentration of the second region.

9. The diode of claim 7 , wherein a third dopant concentration of the third region is greater than a first dopant concentration of the first region.

10. The diode of claim 7 , wherein:

the first region comprises an anode region;

the second region comprises a cathode region; and

the third region comprises an anode enhancement region.

11. The diode of claim 1 , wherein the third region laterally circumscribes the first region and the second region.

12. The diode of claim 1 , wherein a lateral dimension of one of the first region and the second region is different from that lateral dimension of the third region.

13. A diode comprising:

an anode region having a first conductivity type;

a cathode region having a second conductivity type, the cathode region being adjacent to the anode region to provide a first junction between the anode region and the cathode region; and

a third region adjacent to the anode region and the cathode region to provide a second junction between the third region and one of the anode region or the cathode region, wherein the second junction is configured to increase a reverse breakdown voltage of the first junction by increasing a width of a depletion region associated with the first junction within the one of the anode region or the cathode region.

14. The diode of claim 13 , wherein:

the first junction comprises a vertical junction between the anode region and the cathode region;

the second junction comprises a lateral junction between the third region and the one of the anode region or the cathode region; and

the lateral junction influences a reverse breakdown voltage of the vertical junction.

15. The diode of claim 13 , wherein:

the first junction comprises a lateral junction between the anode region and the cathode region;

the second junction comprises a vertical junction between the third region and the one of the anode region or the cathode region; and

the vertical junction influences a reverse breakdown voltage of the lateral junction.

16. The diode of claim 13 , wherein a dopant concentration of the third region is greater than a dopant concentration of the one of the anode region or the cathode region.

17. The diode of claim 13 , wherein the third region has the second conductivity type to provide the second junction between the third region and the anode region.

18. The diode of claim 13 , wherein the third region has the first conductivity type to provide the second junction between the third region and the cathode region.

19. A method of fabricating a diode structure on a semiconductor substrate, the method comprising:

forming a first region in the semiconductor substrate, the first region having a first conductivity type;

forming a second region in the semiconductor substrate adjacent to the first region, the second region having a second conductivity type to provide a first junction between the first region and the second region; and

forming a third region in the semiconductor substrate adjacent to the first region and the second region, the third region providing a second junction between the third region and one of the first region or the second region that influences a reverse breakdown voltage of the first junction.

20. The method of claim 19 , wherein forming the third region comprises implanting ions having a dopant concentration that is greater than a dopant concentration of the one of the first region or the second region.

Assignments (13)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2015
From: CHEN, WEIZE; LIN, XIN; PARRIS, PATRICE M.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 036187/0177 →
Continuity (2)
Continuation 14098194 · Dec 5, 2013
Related Publication 20150333189A1 · Nov 19, 2015