IP Library Granted Patent US 9,368,476
Granted Patent B2
US 9,368,476 · App. 14/811,177 · Granted Jun 14, 2016

Stacked microelectronic assembly with TSVs formed in stages with plural active chips

Inventors: Vage Oganesian (Sunnyvale, CA); Belgacem Haba (Saratoga, CA); Ilyas Mohammed (San Jose, CA); Craig Mitchell (San Jose, CA); Piyush Savalia (San Jose, CA)
Assignee: Tessera, Inc.
H01L25/00H01L21/76898H01L23/3178H01L23/481H01L24/81H01L24/92H01L24/94H01L25/0657H01L25/50H01L2224/0401H01L2224/05009H01L2224/13025H01L2224/16225H01L2224/2919H01L2224/29109H01L2224/29111H01L2224/29144H01L2224/29188H01L2224/32145H01L2224/32245H01L2224/73253H01L2224/83005H01L2224/9202H01L2224/94H01L2225/06513H01L2225/06527H01L2225/06541H01L2924/1032H01L2924/1037H01L2924/10253H01L2924/12042H01L2924/14H01L2924/1433H01L2924/1436H01L2924/1437H01L2924/15311
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Quick Facts
Patent No.
US 9,368,476
App. No.
14/811,177
Granted
Jun 14, 2016
Kind
B2
Abstract

A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle.

Claims (16)

1. A method of fabricating a microelectronic assembly, comprising:

(a) assembling a first microelectronic element with a second microelectronic element such that a first surface of the first microelectronic element faces a first surface of the second microelectronic element, each of the microelectronic elements embodying active semiconductor devices, such that an electrically conductive pad exposed at the first surface of one of the microelectronic elements is juxtaposed with a first electrically conductive element exposed at the first surface of another of the microelectronic elements; and

(b) then forming a second electrically conductive element extending within a first opening extending from a second surface of the first microelectronic element towards the first surface thereof, within a second opening extending from the first opening towards the first surface of the first microelectronic element, and within a third opening extending through at least one of the electrically conductive pad or the first electrically conductive element, wherein interior surfaces of the first and second openings extend in first and second directions relative to the first surface respectively defining a substantial angle, the second electrically conductive element contacting the electrically conductive pad and the first electrically conductive element.

2. The method as claimed in claim 1 , wherein the electrically conductive pad is a first electrically conductive pad exposed at the first surface of the first microelectronic element and the second microelectronic element includes a second electrically conductive pad spaced in a direction along the first surface of the second microelectronic element from the first electrically conductive pad, and the first electrically conductive element extends along the first surface of the second microelectronic element and is electrically coupled with the second electrically conductive pad.

3. The method as claimed in claim 2 , wherein the second electrically conductive element extends through the first electrically conductive pad.

4. The method as claimed in claim 2 , wherein the second electrically conductive pad has an upper surface facing in a direction away from the second microelectronic element and the first electrically conductive element contacts at least a portion of the upper surface of the second electrically conductive pad.

5. The method as claimed in claim 4 , further comprising forming the first electrically conductive element in contact with at least a portion of the upper surface of the second electrically conductive pad before step (a).

6. The method as claimed in claim 5 , wherein at least a portion of the first electrically conductive element is an electrically conductive trace extending along the first surface of the second microelectronic element in a direction between the second electrically conductive pad and a location of the second microelectronic element juxtaposed with the first electrically conductive pad.

7. The method as claimed in claim 2 , wherein the third opening extends through the first electrically conductive pad and a portion of the second electrically conductive element further extends within the third opening and contacts the first electrically conductive pad.

8. The method as claimed in claim 1 , wherein the electrically conductive pad is a first electrically conductive pad exposed at the first surface of the second microelectronic element and the first microelectronic element includes a second electrically conductive pad spaced in a direction along the first surface of the first microelectronic element from the first electrically conductive pad, and the first electrically conductive element extends along the first surface of the first microelectronic element and is electrically coupled with the second electrically conductive pad.

9. The method as claimed in claim 8 , wherein the second electrically conductive element extends through the first electrically conductive pad.

10. The method as claimed in claim 8 , wherein the second electrically conductive pad has an upper surface facing in a direction away from the second microelectronic element and the first electrically conductive element contacts at least a portion of the upper surface of the second electrically conductive pad.

11. The method as claimed in claim 10 , further comprising forming the first electrically conductive element in contact with at least a portion of the upper surface of the second electrically conductive pad before step (a).

12. The method as claimed in claim 11 , wherein at least a portion of the first electrically conductive element is an electrically conductive trace extending along the surface of the first microelectronic element in a direction between the second electrically conductive pad and a location of the first microelectronic element juxtaposed with the first electrically conductive pad.

13. The method as claimed in claim 8 , wherein a portion of the second conductive element further extends within an opening extending from a second surface of the second microelectronic element through the second electrically conductive pad.

14. The method as claimed in claim 1 , further comprising assembling a third microelectronic element with the first and second microelectronic elements such that a first surface of the third microelectronic element faces a second surface of the second microelectronic element, and then forming a third electrically conductive element extending within at least an opening extending from a second surface of the third microelectronic element, the third electrically conductive element extending through an electrically conductive pad of the third microelectronic element and contacting the second electrically conductive element.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0373 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0816 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2015
From: OGANESIAN, VAGE; HABA, BELGACEM; MOHAMMED, ILYAS; MITCHELL, CRAIG; SAVALIA, PIYUSH
To: TESSERA, INC.
Reel/Frame 037225/0150 →
Continuity (4)
Division 14060997 · Oct 23, 2013
Division 13051414 · Mar 18, 2011
Provisional Application 61419037 · Dec 2, 2010
Related Publication 20150333050A1 · Nov 19, 2015