High doped III-V source/drain junctions for field effect transistors
View Patent ↗A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e 18 to about 1e 20 atoms/cm 3 and contacting the epitaxial contacts.
1. A semiconductor device, comprising:
a fin patterned in a substrate;
a gate disposed over and substantially perpendicular to the fin;
a pair of epitaxial contacts comprising a III-V material over the fin and on opposing sides of the gate; and
a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials comprising a dopant in an amount in a range from about 1e 18 to about 1e 20 atoms/cm 3 and contacting the epitaxial contacts.
2. The semiconductor device of claim 1 , wherein the dopant is an n-type dopant or a p-type dopant.
3. The semiconductor device of claim 1 , wherein the gate comprises spacers along sidewalls of the gate.
4. The semiconductor device of claim 3 , wherein the doped III-V material is positioned under the gate between the spacers and the substrate.
5. The semiconductor device of claim 1 , further comprising a buffer layer between the channel region and the substrate.
6. The semiconductor device of claim 5 , wherein the buffer layer comprises copper doped silicon.
7. The semiconductor device of claim 1 , wherein the buffer layer has a thickness in a range from about 30 to about 150 nm.
8. The semiconductor device of claim 1 , wherein the epitaxial contacts are formed over recesses within the substrate.