IP Library Granted Patent US 9,754,825
Granted Patent B2
US 9,754,825 · App. 14/815,560 · Granted Sep 5, 2017

Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Inventors: Hongqi Li (Boise, ID); Anurag Jindal (Boise, ID); Jin Lu (Boise, ID); Shyam Ramalingam (Boise, ID)
Assignee: Micron Technology, Inc.
H01L21/76879H01L21/2885H01L21/76841H01L21/76898H01L23/481H01L2924/0002
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Quick Facts
Patent No.
US 9,754,825
App. No.
14/815,560
Granted
Sep 5, 2017
Kind
B2
Abstract

Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Claims (37)

1. A method of manufacturing a semiconductor device, comprising:

partially filling an opening in a substrate with a first material, wherein the first material has a positive coefficient of thermal expansion (CTE); and

further filling the opening with a second material, wherein the second material has a negative CTE,

wherein the first material is between the substrate and the second material.

2. The method of claim 1 wherein:

partially filling the opening with the first material comprises plating a conductive material onto a sidewall of the opening; and

further filling the opening with the second material comprises depositing a negative thermal expansion material (NTE) onto at least a portion the conductive material in the opening.

3. The method of claim 2 wherein the conductive material is a first conductive material, and wherein the method further comprises:

removing a portion of the NTE material from the opening; and

after removing the portion of the NTE material, further filling the opening with a second conductive material.

4. The method of claim 3 , further comprising removing material from the substrate such that at least the first material extends completely through the substrate.

5. The method of claim 3 , further comprising forming an interconnect, wherein the interconnect includes the first and second materials.

6. A method of manufacture, comprising forming an interconnect structure, wherein:

the interconnect structure includes a conductive material and a negative thermal expansion (NTE) material within at least a portion of the conductive material; and

the interconnect structure has a composite coefficient of thermal expansion (CTE) based, at least in part, on a volume of the NTE material within the conductive material.

7. The method of claim 6 wherein:

the conductive material has a coefficient of thermal expansion (CTE) that is greater than zero;

the NTE material has a CTE that is less than zero.

8. The method of claim 6 , further comprising forming a volume of the conductive material on a semiconductor substrate, wherein the volume of the conductive material is based on the composite CTE.

9. The method of claim 8 wherein the interconnect structure includes at least one of a contact pad and a conductive trace.

10. The method of claim 6 wherein forming the interconnect structure further comprises forming at least a portion of the interconnect structure within an opening in a semiconductor substrate.

11. The method of claim 6 wherein a volume of the opening is based on the composite CTE.

12. The method of claim 10 wherein the interconnect structure includes a conductive via.

13. A method of manufacture, comprising forming an interconnect structure:

disposing a first material in an opening in a substrate,

wherein the first material has a positive coefficient of thermal expansion (CTE); and

disposing a second material in the opening in the substrate,

wherein the second material has a negative CTE, and

wherein the first material is between the substrate and the second material.

14. The method of claim 13 wherein:

disposing the first material in the opening comprises plating a conductive material onto a sidewall of the opening; and

disposing the second material in the opening comprises depositing a negative thermal expansion material (NTE) onto at least a portion the conductive material in the opening.

15. The method of claim 13 wherein: the first material includes copper, and the second material includes Zr(WO 4 ) 2 .

16. The method of claim 13 wherein: the second material includes ZrV 2 O 7 .

17. The method of claim 13 wherein: the second material includes ZrMo 2 O 8 , ZrW 2 O 8 , HfMo 2 O 8 , or HfW 2 O 8 , or a combination thereof.

18. The method of claim 13 wherein: the second material includes Zr 2 (MoO 4 ) 3 , Zr 2 (WO 4 ) 3 , Hf 2 (MoO 4 ) 3 , Hf 2 (WO 4 ) 3 , or a combination thereof.

19. The method of claim 13 wherein: the first material includes at least one of copper, aluminum, tungsten, silver, gold, and platinum.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 13959429 · Aug 5, 2013
Related Publication 20150340282A1 · Nov 26, 2015