Method and system for planar regrowth in GaN electronic devices
View Patent ↗A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.
1. A vertical JFET comprising:
a III-nitride substrate; and
a III-nitride epitaxial structure coupled to the III-nitride substrate, wherein the III-nitride epitaxial structure comprises:
a plurality of channels of a first conductivity type, wherein each of the channels comprises an interface surface,
a plurality of sources of the first conductivity type, wherein each of the sources comprises a contact surface contacting an interface surface of the channels, and
a plurality of epitaxially grown gates interleaved with the channels, wherein an upper surface of the gates is substantially coplanar with the contact surfaces of the sources.
2. The vertical JFET of claim 1 , further comprising:
a plurality of source contacts, wherein each source contact is electrically coupled to one of the sources; and
a plurality of gate contacts, wherein each gate contact is electrically coupled to one of the regrown gates.
3. The vertical JFET of claim 1 , further comprising a drain contact electrically coupled to the III-nitride substrate.
4. The vertical JFET of claim 1 , wherein the first conductivity type is n type and the gates are p type.
5. The vertical JFET of claim 1 , wherein the channels are disposed between the gates such that current flow during operation of the vertical JFET is along a direction orthogonal to the upper surface of the set of regrown gates.
6. The vertical JFET of claim 1 , wherein the III-nitride substrate comprises an n-type substrate.
7. The vertical JFET of claim 1 , wherein a width of the channels measured along a direction orthogonal to a thickness of the III-nitride epitaxial layer is less than 5 μm.
8. The vertical JFET of claim 1 , wherein the gates comprise a p-type III-nitride material.
9. The vertical JFET of claim 1 , wherein the gates are further electrically coupled to a drift region.
10. The vertical JFET of claim 1 , wherein the channels have a first dopant concentration and the gates have a second dopant concentration.
11. The vertical JFET of claim 10 , wherein at least one of the first dopant concentration and the second dopant concentration is non-uniform.
12. A method of manufacturing a vertical JFET, the method comprising:
providing a III-nitride substrate; and
forming a III-nitride epitaxial structure on the III-nitride substrate, wherein the III-nitride epitaxial structure comprises:
a plurality of channels of a first conductivity type, wherein each of the channels comprises an interface surface,
a plurality of sources of the first conductivity type, wherein each of the sources comprises a contact surface contacting an interface surface of the channels, and
a plurality of epitaxially grown gates interleaved with the channels, wherein an upper surface of the gates is substantially coplanar with the contact surfaces of the sources.
13. The method of claim 12 , further comprising:
forming a plurality of source contacts, wherein each source contact is electrically coupled to one of the sources; and
forming a plurality of gate contacts, wherein each gate contact is electrically coupled to one of the regrown gates.
14. The method of claim 12 , further comprising forming a drain contact electrically coupled to the III-nitride substrate.
15. The method of claim 12 , wherein the first conductivity type is n type and the gates are p type.
16. The method of claim 12 , wherein the channels are disposed between the gates such that current flow during operation of the vertical JFET is along a direction orthogonal to the upper surface of the set of regrown gates.
17. The method of claim 12 , wherein the III-nitride substrate comprises an n-type substrate.
18. The method of claim 12 , wherein a width of the channels measured along a direction orthogonal to a thickness of the III-nitride epitaxial layer is less than 5 μm.
19. The method of claim 12 , wherein the gates comprise a p-type III-nitride material.
20. The method of claim 12 , wherein the gates are further electrically coupled to a drift region.
21. The method of claim 12 , wherein the channels have a first dopant concentration and the gates have a second dopant concentration.
22. The method of claim 21 , wherein at least one of the first dopant concentration and the second dopant concentration is non-uniform.