Resistive switching memory having a resistor, diode, and switch memory cell

1. A semiconductor memory device, comprising a plurality of resistive switching memory cells, wherein each resistive switching memory cell comprises:

a) a programmable impedance element having an anode and a cathode;

b) an access transistor having a drain coupled to a bit line, a source coupled to the programmable impedance element cathode, and a gate coupled to a word line;

c) a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and

d) a diode having a cathode at the first diffusion region, and an anode at the third diffusion region, wherein the diode is turned on during an erase operation on the programmable impedance element.

2. The semiconductor memory device of claim 1 , wherein the diode is turned off during a program operation on the programmable impedance element.

3. The semiconductor memory device of claim 1 , wherein the diode is turned off during a read operation on the programmable impedance element.

4. The semiconductor memory device of claim 1 , wherein the word line is turned off during the erase operation on the programmable impedance element.

5. The semiconductor memory device of claim 1 , wherein each programmable impedance element anode is connected together for the plurality of resistive switching memory cells.

6. The semiconductor memory device of claim 1 , wherein:

a) each of the first and second diffusion regions comprises an N+ region; and

b) the third diffusion region comprises a P+ region.

7. The semiconductor memory device of claim 6 , wherein the well comprises a P-type well.

8. The semiconductor memory device of claim 7 , further comprising an N-type well, wherein the P-type well is disposed within the N-type well.

9. The semiconductor memory device of claim 1 , wherein the well is disposed along a subset of the plurality of resistive switching memory cells having a common word line.

10. The semiconductor memory device of claim 1 , wherein the plurality of resistive switching memory cells are formed in a triple well process.

11. The semiconductor memory device of claim 1 , wherein the plurality of resistive switching memory cells are formed in a silicon on insulator (SOI) process.

12. The semiconductor memory device of claim 1 , wherein the programmable impedance element comprises:

a) an inert electrode coupled to a first side of a solid electrolyte;

b) an active electrode coupled to a second side of the solid electrolyte, wherein the programmable impedance element is programmed by formation of a conductive path between the active and inert electrodes; and

c) a plurality of mobile elements derived from the active electrode, wherein the plurality of mobile elements are reduced in the solid electrolyte to form the conductive path.

13. The semiconductor memory device of claim 12 , wherein the conductive path in the programmable impedance element is formed by application of a first voltage across the active and inert electrodes, the conductive path remaining once formed after the first voltage is removed.

14. The semiconductor memory device of claim 12 , wherein at least a portion of the conductive path is dissolved to erase the programmable impedance element by application of a second voltage across the active and inert electrodes.

15. A method of controlling a resistive switching memory cell, the method comprising:

a) determining if a command to executed on the resistive switching memory cell is a read operation, a program operation, or an erase operation, wherein the resistive switching memory cell comprises: a programmable impedance element having an anode and a cathode; an access transistor having a drain coupled to a bit line, a source coupled to the programmable impedance element cathode, and a gate coupled to a word line; a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and a diode having an anode at the second diffusion region, and a cathode at the third diffusion region;

b) turning on the word line for the program operation and the read operation;

c) turning off the word line for the erase operation; and

d) turning on the diode for the erase operation.

16. The method of claim 15 , further comprising turning the diode off for the program operation and the read operation.

17. The method of claim 15 , wherein the turning on the diode for the erase operation comprising applying a high level on the well contact.

18. The method of claim 15 , wherein the erase operation comprises a block erase.

19. A semiconductor memory device, comprising a plurality of resistive switching memory cells, wherein each resistive switching memory cell comprises:

a) a programmable impedance element having an anode and a cathode;

b) an access transistor having a source coupled to a bit line, a drain coupled to the programmable impedance element anode, and a gate coupled to a word line;

c) a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and

d) a diode having an anode at the first diffusion region, and a cathode at the third diffusion region, wherein the diode is turned on during an erase operation on the programmable impedance element.

20. The semiconductor memory device of claim 19 , wherein the word line is turned off during the erase operation on the programmable impedance element.