Three-dimensional integrated circuit structure and bonded structure
View Patent ↗Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first chip, a second chip and at least one through substrate via (TSV). The first chip is electrically connected to the second chip with a first bonding pad of the first chip and a second bonding pad of the second chip. The TSV extends from a first backside of the first chip to a metallization element of the first chip. At least one conductive via is electrically connected between the TSV and the first bonding pad, and at least one elongated slot or closed space is within the at least one conductive via.
1. A three-dimensional integrated circuit structure, comprising:
a first chip electrically connected to a second chip with a first bonding pad of the first chip and a second bonding pad of the second chip; and
at least one through substrate via (TSV), extending from a first backside of the first chip to a metallization element of the first chip,
wherein at least one conductive via is electrically connected between the TSV and the first bonding pad, and at least one elongated slot or closed space, from a top view, is within the at least one conductive via.
2. The three-dimensional integrated circuit structure of claim 1 , wherein the metallization element is a metal line the closest to the first backside of the first chip.
3. The three-dimensional integrated circuit structure of claim 1 , wherein the metallization element is a metal gate of the first chip.
4. The three-dimensional integrated circuit structure of claim 1 , further comprising a dielectric material filling the at least one elongated slot or closed space within the at least one conductive via.
5. The three-dimensional integrated circuit structure of claim 1 , wherein a first area of the TSV exposed by the first backside is smaller than a second area of the TSV contacting the metallization element of the first chip.
6. The three-dimensional integrated circuit structure of claim 5 , wherein a first area of the TSV exposed by the first backside is greater than a second area of the TSV contacting the metallization element of the first chip.
7. The three-dimensional integrated circuit structure of claim 1 , wherein the at least one conductive via comprises a plurality of conductive vias formed as walls substantially parallel to each other.
8. The three-dimensional integrated circuit structure of claim 1 , wherein the at least one conductive via comprises a plurality of conductive vias formed as concentric rings.
9. The three-dimensional integrated circuit structure of claim 1 , wherein the at least one conductive via has a fence shape.
10. A three-dimensional integrated circuit structure, comprising:
a first chip bonded to a second chip through a hybrid bonding comprising a metal-to-metal bonding and a dielectric-to-dielectric bonding; and
at least one through substrate via (TSV) penetrating through a first substrate of the first chip and electrically connected to the second chip with a plurality of stripe-shaped conductive vias.
11. The three-dimensional integrated circuit structure of claim 10 , wherein the stripe-shaped conductive vias are separated from each other.
12. The three-dimensional integrated circuit structure of claim 10 , wherein at least a portion of the stripe-shaped conductive vias are connected.
13. The three-dimensional integrated circuit structure of claim 10 , wherein the stripe-shaped conductive vias are formed as walls, fences, rings or a combination thereof.
14. The three-dimensional integrated circuit structure of claim 10 , wherein the TSV is landed on a metal line closest to the first substrate of the first chip.
15. The three-dimensional integrated circuit structure of claim 10 , wherein the TSV is landed on a metal gate of the first chip.
16. A three-dimensional integrated circuit structure, comprising:
a first chip bonded to a second chip; and
at least one through substrate via (TSV) penetrating through a first substrate of the first chip and landed on a metal gate of the first chip.
17. The three-dimensional integrated circuit structure of claim 16 , wherein the first chip comprises, over the first substrate, a plurality of conductive layers and a plurality of conductive vias between two adjacent conductive layers and electrically connected to the TSV.
18. The three-dimensional integrated circuit structure of claim 17 , wherein the conductive vias are formed as pillars, walls, fences, rings or a combination thereof.
19. The three-dimensional integrated circuit structure of claim 17 , wherein the first chip further comprises a plurality of stripe-shaped conductive vias electrically connected between the metal gate and a conductive layer the closest to the metal gate.
20. The three-dimensional integrated circuit structure of claim 19 , wherein the stripe-shaped conductive vias are formed as walls, fences, rings or a combination thereof.