IP Library Granted Patent US 9,419,084
Granted Patent B2
US 9,419,084 · App. 14/840,744 · Granted Aug 16, 2016

Devices, components and methods combining trench field plates with immobile electrostatic charge

Inventors: Mohamed N. Darwish (Campbell, CA); Jun Zeng (Torrance, CA)
Assignee: MaxPower Semiconductor Inc.
H01L29/407H01L29/0638H01L29/1095H01L29/16H01L29/404H01L29/408H01L29/7811H01L29/7813H01L29/7827H01L29/7835H03K17/687H01L29/0634H01L29/0692H01L29/0696H01L29/0847H01L29/0878H01L29/41766H01L29/4236H01L29/42368H01L29/42376
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Quick Facts
Patent No.
US 9,419,084
App. No.
14/840,744
Granted
Aug 16, 2016
Kind
B2
Abstract

N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

Claims (10)

1. A semiconductor device, comprising:

an n-type source, a p-type body region, and an insulated gate electrode which is capacitively coupled to invert portions of said body region and thereby inject electrons into a semiconductor p-type drift region;

a trench, abutting said drift region, which contains at least one conductive field plate, and which also contains immobile net electrostatic charge in a concentration sufficient to invert portions of said p-type drift region in proximity to said trench; and

an n-type drain region underlying said drift region;

wherein said field plate has sidewalls which are predominantly vertical and parallel to a sidewall of said trench;

wherein said drift region consists essentially of silicon.

2. The device of claim 1 , wherein each said trench includes only one said field plate.

3. The device of claim 1 , comprising a plurality of said trenches.

4. The device of claim 1 , wherein said field plate is heavily doped polysilicon.

5. The device of claim 1 , wherein said drift region includes paralleled p-type and n-type regions.

Assignments (1)
SECURITY INTEREST Recorded Dec 27, 2022
From: MAXPOWER SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 062228/0648 →
Continuity (5)
Continuation 13975421 · Aug 26, 2013
Continuation 13004054 · Jan 11, 2011
Provisional Application 61294427 · Jan 12, 2010
Provisional Application 61307007 · Feb 23, 2010
Related Publication 20160064497A1 · Mar 3, 2016