Electric field sensor, system, and method for programming electronic devices on a wafer
An electric field sensor includes sense and reference cells. The sense cell produces a resistance that varies relative to an intensity of an electric field, and the reference cell produces a resistance that is invariable relative to the intensity of the electric field. An output signal indicative of the intensity of the electric field is determined using the difference between the resistances. A system includes an electric field source that outputs a digital test program as an electric field signal. The system further includes the electric field sensor formed with IC dies on a wafer. The electric field sensor receives the electric field signal. The received electric field signal is converted to the test program, and the test program is stored in memory on the wafer. The electric field source does not physically contact the dies, but can flood an entire surface of the wafer with the electric field signal.
1. A system for programming integrated circuit (IC) dies formed on a wafer comprising:
an electric field source configured to output a digital program as an electric field signal;
an electric field sensor formed with said IC dies of said wafer, said electric field sensor being configured to receive said electric field signal from said electric field source and produce an output signal indicative of an intensity of said electric field signal;
a processor formed on said wafer and in communication with said electric field sensor, said processor being adapted to convert said output signal to said digital program; and
a memory element associated with one of said IC dies on said wafer, said memory element being adapted to store said digital program, wherein said one of said IC dies includes a built-in self-test (BIST) mechanism to determine said functionality of said one of said IC dies, said processor is configured to communicate with said BIST mechanism, and said processor is further configured to execute said digital program, wherein execution of said digital program initiates operation of said BIST mechanism and receipt of a test result from said BIST mechanism, said test result being result indicative of a functionality of said one of said IC dies.
2. The system of claim 1 wherein said electric field source does not physically contact said IC dies.
3. The system of claim 1 wherein said electric field source is adapted to modulate said digital program as a sequence of pulses, said sequence of pulses forming said electric field signal.
4. The system of claim 1 wherein said electric field source is configured to flood an entire surface of said wafer with said electric field signal.
5. The system of claim 1 wherein said electric field sensor comprises:
a sense cell adapted to produce a first resistance which varies in accordance with an intensity of said electric field signal; and
a reference cell adapted to produce a second resistance that is substantially invariable relative to said intensity of said electric field signal, wherein said output signal is determined in response to a difference between said first resistance and said second resistance.
6. The system of claim 5 wherein said sense cell is a first sense cell, said reference cell is a first reference cell, and said electric field sensor further comprises:
a second sense cell adapted to produce a third resistance which varies in accordance with said intensity of said electric field signal; and
a second reference cell adapted to produce a fourth resistance that is substantially invariable relative to said intensity of said electric field signal, wherein said first sense cell, said first reference cell, said second sense cell, and said second reference cell are connected to define a Wheatstone bridge circuit.
7. The system of claim 5 wherein said sense cell includes a first source region, a first drain region, a first gate region, and a first resistance channel electrically interconnecting said first source region with said first drain region, said first resistance channel having said first resistance, wherein said first gate region is coupled to ground prior to detection of said first resistance and following coupling, said gate region is decoupled from said ground prior to detection of said first resistance.
8. The system of claim 1 wherein electric field sensor is one of a plurality of electric field sensors, one each of said electric field sensors being formed with one each of said IC dies of said wafer.
9. A system for programming integrated circuit (IC) dies formed on a wafer comprising:
a wafer test unit having a probe card, an electric field source, and a probe element coupled to said probe card, wherein said electric field source is configured to output a digital program as an electric field signal, and said probe element provides source power;
a probe pad on said wafer and electrically coupled with said IC dies, said probe element being configured for touchdown on said probe pad to selectively provide said source power to each of said IC dies;
an electric field sensor formed with said IC dies of said wafer, said electric field sensor being configured to receive said electric field signal from said electric field source and produce an output signal indicative of an intensity of said electric field signal;
a processor formed on said wafer and in communication with said electric field sensor, said processor being adapted to convert said output signal to said digital program; and
a memory element associated with one of said IC dies on said wafer, said memory element being adapted to store said digital program, wherein said processor is further configured to execute said digital program, receive a test result indicative of a functionality of said one of said IC dies, and modulate said source power in accordance with said test result to return said test result to said wafer test unit.
10. A method of programming integrated circuit (IC) dies formed on a wafer comprising:
transmitting a digital program as an electric field signal from an electric field source;
receiving said electric field signal from said electric field source at an electric field sensor formed with said IC dies of said wafer, said electric field sensor including a sense cell and a reference cell, said sense cell being adapted to produce a first resistance which varies in accordance with an intensity of said electric field signal, and said reference cell being adapted to produce a second resistance that is substantially invariable relative to said intensity of said electric field signal, wherein an output signal indicative of said intensity of said electric field signal is determined in response to a difference between said first resistance and said second resistance;
converting said output signal to said digital program at a processor formed on said wafer and in communication with said electric field source;
storing said digital program in a memory element associated with one of said IC dies on said wafer, wherein said one of said IC dies includes a built-in self-test (BIST) mechanism to determine a functionality of said one of said IC dies; and
executing, at said processor, said digital program, wherein execution of said digital program initiates operation of said BIST mechanism and receipt of a test result from said BIST mechanism, said test result being indicative of a functionality of said one of said IC dies.
11. The method of claim 10 further comprising:
fabricating said wafer to include a plurality of subsystems, one each of said subsystems being formed with one each of said IC dies of said wafer, each of said subsystems comprising said electric field sensor, said processor in communication with said electric field sensor, and said memory element in communication with said processor; and
flooding an entire surface of said wafer with said electric field signal such that each of said subsystems concurrently receives said electric field signal, converts said electric field signal to said digital program, and stores said digital program in association with said one each of said IC dies.
12. The method of claim 10 wherein said sense cell includes a source region, a drain region, a gate region, and a resistance channel electrically interconnecting said source region with said drain region, said resistance channel having said first resistance, and said method comprises:
coupling said gate region to ground prior to producing said first resistance; and
following said coupling, decoupling said gate region from said ground prior to producing said first resistance, said coupling and decoupling operations substantially removing surface charge from a surface of said wafer.
13. The method of claim 10 further comprising:
providing source power via a wafer test unit; and
selectively providing said source power to each of said IC dies by touchdown of said probe element onto a probe pad on said wafer, said probe pad being electrically coupled with said IC dies.
14. The method of claim 13 further comprising:
a wafer test unit having a probe card, said electric field source and a probe element being coupled to said probe card, wherein said probe element provides source power; and
a probe pad on said wafer and electrically coupled with said IC dies, said probe element being configured for touchdown on said probe pad to selectively provide said source power to each of said IC dies, wherein said processor is further configured to execute said digital program, receive a test result indicative of a functionality of said one of said IC dies; and
modulating said source power at said processor in accordance with said test result to return said test result to said wafer test unit.