Method of manufacturing non volatile memory device
View Patent ↗A non-volatile memory device includes a semiconductor substrate, a well region situated on the semiconductor substrate, a floating gate situated on the well region, a floating gate channel region, a control gate situated on both sides of the floating gate, a control gate channel region, and an ion implantation area for regulating a program threshold voltage integrally formed between an area underneath of the floating gate and the control gate and a foreside of the well region, wherein a doping concentration of the ion implantation area for regulating a program threshold voltage is greater than a doping concentration of the well region. Therefore, the non-volatile memory device of examples integrally forms an ion implantation area for regulating a program threshold voltage irrespective of a channel region of a floating gate and a control gate so as to guarantee durability of a non-volatile memory device.
1. A non-volatile memory device, comprising:
a semiconductor substrate;
a well region of a first conductivity type situated on the semiconductor substrate;
dopant implanted into an ion implantation area, the ion implantation area situated in the well region;
a floating gate situated on the well region;
a control gate situated on both sides of the floating gate;
a tunnel oxide film situated between the floating gate and the ion implantation area;
a dielectric film situated between the floating gate and the control gate, wherein the dielectric film is formed to be in contact with a sidewall of the floating gate and a sidewall of the tunnel oxide film; and
a gate insulator film disposed between the control gate and the ion implantation area, wherein a thickness of the gate insulator film is smaller than a thickness of the dielectric film.
2. The non-volatile memory device of claim 1 , further comprising:
a shallow trench isolation (STI) region situated a side of the semiconductor substrate, wherein a depth of the STI region is shallower than a depth of the well region; and
a source-drain region exposed at a side of the control gate and situated in the well region, wherein the source-drain region is overlapped with the control gate.
3. The non-volatile memory device of claim 2 , wherein a depth of the ion implantation area is shallower than a depth of the source-drain region.
4. The non-volatile memory device of claim 1 , wherein the ion implantation area comprises a floating gate channel region and a control gate channel region.
5. The non-volatile memory device of claim 4 , wherein an increased dose of dopant is implanted into the ion implantation area to cause a voltage level difference between a program voltage and an erase voltage.
6. The non-volatile memory device of claim 5 , wherein a voltage level of the program voltage is within a range of 3.5V and 6V and a voltage level of the erase voltage is within a range of 1V and 2.5V.
7. The non-volatile memory device of claim 1 , wherein the dopant implanted into the ion implantation area is formed with a dose in a range of 1E11 ions/cm 2 and 1E14 ions/cm 2 .
8. A method of manufacturing a non-volatile memory device, comprising:
forming a shallow trench isolation (STI) region and an active region on a semiconductor substrate;
forming a well region in the active region of a first conductivity type;
implanting a dopant into the active region to form an ion implantation area, the ion implantation area being situated in the well region;
forming a tunnel oxide film on the ion implantation area;
forming a floating gate on the tunnel oxide film;
forming a dielectric film to envelop the floating gate, wherein the dielectric film is formed to be in contact with a sidewall of the floating gate and a sidewall of the tunnel oxide film;
forming a control gate to surround the dielectric film; and
forming a source-drain region, exposed at a side of the control gate, on the well region, wherein the source-drain region is overlapped with the control gate.
9. The method of manufacturing a non-volatile memory device of claim 8 , wherein a doping concentration of the ion implantation area is greater than a doping concentration of the well region.
10. The method of manufacturing a non-volatile memory device of claim 8 , wherein the ion implantation area is situated in an area underneath of the floating gate and the control gate.
11. The method of manufacturing a non-volatile memory device of claim 8 , wherein an increased dose of dopant is implanted into the ion implantation area to cause a voltage level difference between a program voltage and an erase voltage.
12. The method of manufacturing a non-volatile memory device of claim 11 , wherein a voltage level of the program voltage is within a range of 3.5V and 6V and a voltage level of the erase voltage is within a range of 1 V and 2.5V.
13. The method of manufacturing a non-volatile memory device of claim 8 , wherein the dopant implanted into the ion implantation area is formed with a dose in a range of 1E11/cm 2 and 1E14/cm 2 .
14. The method of manufacturing a non-volatile memory device of claim 8 , wherein a depth of the ion implantation area is shallower than a depth of the source-drain region.
15. A non-volatile memory device, comprising:
a floating gate situated on a well region situated on a semiconductor substrate;
a control gate situated on both sides of the floating gate;
dopant implanted into an ion implantation area, the ion implantation area situated between an area underneath of the floating gate and the control gate and a foreside of the well region;
a tunnel oxide film situated between the floating gate and the ion implantation area; and
a dielectric film situated between the floating gate and the control gate, wherein the dielectric film is formed to be in contact with a sidewall of the floating gate and a sidewall of the tunnel oxide film; and
a gate insulator film disposed between the control gate and the ion implantation area,
wherein a thickness of the gate insulator film is smaller than a thickness of the dielectric film.
16. The non-volatile memory device of claim 15 , further comprising:
a shallow trench isolation (STI) region situated a side of the semiconductor substrate, wherein a depth of the STI region is shallower than a depth of the well region; and
a source-drain region exposed at a side of the control gate and situated in the well region, wherein the source-drain region is overlapped with the control gate.
17. The non-volatile memory device of claim 16 , wherein a depth of the ion implantation area is shallower than a depth of the source-drain region.
18. The non-volatile memory device of claim 15 , wherein a voltage level difference between a program voltage and an erase voltage is increased by providing an increased dose of dopant implanted into the ion implantation area.
19. The non-volatile memory device of claim 1 , further comprising another well region of a second conductivity type situated between the semiconductor substrate and the well region.
20. The non-volatile memory device of claim 15 , further comprising another well region of a second conductivity type situated between the semiconductor substrate and the well region.
21. The method of manufacturing a non-volatile memory device of claim 8 , further comprising:
forming a gate insulator film on the well region, and
wherein the gate insulator film is disposed between the control gate and the ion implantation area, wherein a thickness of the gate insulator film is smaller than a thickness of the dielectric film situated between the floating gate and the control gate.
22. The method of manufacturing a non-volatile memory device of claim 8 , further comprising:
forming a lightly doped drain region after forming the control gate.