Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same
Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
1. A semiconductor package, comprising:
a substrate;
a main stacked dies (MSD) structure comprising a substantially horizontal arrangement of a plurality of semiconductor dies interconnected to the substrate;
one or more vertical side chips electrically coupled directly to the MSD structure and interconnected to the substrate;
one or more vertical side chips electrically coupled directly to the MSD structure but not interconnected to the substrate; and
an underfill material disposed between the substrate and the MSD structure, between the substrate and the one or more vertical side chips interconnected to the substrate, and between the substrate and the one or more vertical side chips not interconnected to the substrate.
2. The semiconductor package of claim 1 , wherein the one or more vertical side chips not interconnected, to the substrate comprises three vertical side chips not interconnected to the substrate.
3. The semiconductor package of claim 1 , wherein one of the one or more vertical side chips interconnected to the substrate is interconnected to the substrate via a die side pad (DSP) of the one of the one or more vertical side chips interconnected to the substrate.
4. The semiconductor package of claim 1 , wherein one of the one or more vertical side chips interconnected to the substrate is coupled to the MSD structure via one or more front interconnections of the one of the one or more vertical side chips interconnected to the substrate, the front interconnections disposed on an active side of the one of the one or more vertical side chips interconnected to the substrate.
5. The semiconductor package of claim 4 , wherein a front interconnection of the one of the one or more vertical side chips interconnected to the substrate is coupled to the MSD structure via a DSP of the MSD structure.
6. The semiconductor package of claim 4 , wherein a front interconnection of the one of the one or more vertical side chips interconnected to the substrate is coupled to the MSD structure via an end of metal routing of a die in the MSD structure.
7. The semiconductor package of claim 1 , wherein one of the one or more vertical side chips interconnected to the substrate comprises one or more through silicon vias (TSVs).