Semiconductor memory device for storing multivalued data
Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
1. A semiconductor memory device comprising:
a memory cell array in which memory cells is provided in a matrix;
word lines connected to the memory cells;
bit lines connected to the memory cells;
a control circuit configured to control potentials of the word lines and potentials of bit lines,
a constant voltage generation circuit,
wherein data in an n number of memory cells among the memory cells is simultaneously read from memory cell array;
an h (2<h<n) number of memory cells among the n number of memory cells is used as flag cells, data of the flag cells is determined by a majority decision for the read data from the h number of memory cells, and
in a read result of a k (k<n) number of memory cells among the read n number of memory cells,
the read data from the k number of memory cells is converted based on data of the flag cells determined by a majority decision.
2. The semiconductor memory device according to claim 1 , wherein
write data is simultaneously written into the n number of memory cells in a write operation.
3. The semiconductor memory device according to claim 1 , wherein
data from an external is written into the k number of memory cells.
4. The semiconductor memory device according to claim 1 , wherein
data read from the k number of memory cells is outputted to an external.
5. The semiconductor memory device according to claim 1 , wherein
data read from the h number of memory cells as the flag cells is not outputted to an external.
6. The semiconductor memory device according to claim 1 , wherein
when the data of the flag cells determined by the majority decision is a first value, the read data from the k number of memory cells is set to a second value.
7. The semiconductor memory device according to claim 1 , wherein
each of the h number of memory cells is capable of storing the data having a third value or a fourth value, a result of the majority decision is determined based on the number of the third values.
8. The semiconductor memory device according to claim 1 , wherein
each of the memory cells is capable of storing i bits of data (i is a natural number equal to or larger than two).