Semiconductor memory device
View Patent ↗A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.
1. A method of controlling a magnetoresistive random access memory, comprising:
receiving an active command through command/address pins at a rising edge and a falling edge of a clock signal, the active command specifying a first set of row addresses;
receiving a read command, after receiving the active command, through the command/address pins at a rising edge and a falling edge of the clock signal, the read command specifying column addresses and a second set of row addresses;
reading data from at least one of memory cells, in response to receiving the read command, according to the first set of row addresses and the second set of row addresses associated with the read command;
receiving a write command through the command/address pins at a rising edge and a falling edge of the clock signal, while reading the data from the at least one of memory cells, the write command specifying column addresses and a second set of row addresses;
outputting the data read from the at least one of memory cells to data input/output pins, according to the column addresses associated with the read command, after a lapse of a predetermined read latency from receiving the read command;
receiving data through the data input/output pins, according to the column addresses associated with the write command, after a lapse of a predetermined write latency from receiving the write command; and
writing the data inputted from the data input/output pins to at least one of memory cells according to the first set of row addresses and the second set of row addresses associated with the write command.
2. The method according to claim 1 , further comprising:
reading data from the at least one of memory cells to be written, in response to receiving the write command, before writing the data inputted from the data input/output pins to the at least one of memory cells.
3. The method according to claim 1 , wherein a timing of using the column addresses is delayed by a predetermined period in comparison with a timing of using the first and second sets of row addresses.
4. The method according to claim 3 , wherein shift registers connected in series are used to generate the delay.
5. The method according to claim 1 , wherein a period of the read latency and a period of the write latency are different from each other.
6. The method according to claim 5 , wherein the period of the read latency is longer than the period of the write latency.
7. The method according to claim 1 , wherein there is a time lag between outputting the data read from the at least one of memory cells to the data input/output pins and receiving the data through the data input/output pins.
8. A method of controlling a magnetoresistive random access memory, comprising:
receiving an active command through command/address pins at a rising edge and a falling edge of a clock signal, the active command specifying a first set of row addresses;
receiving a write command, after receiving the active command, through the command/address pins at a rising edge and a falling edge of the clock signal, the write command specifying column addresses and a second set of row addresses;
reading data from at least one of memory cells to be written, in response to receiving the write command;
receiving a read command through the command/address pins at a rising edge and a falling edge of the clock signal, while reading the data from the at least one of memory cells, the read command specifying column addresses and a second set of row addresses;
reading data from at least one of memory cells, in response to receiving the read command, according to the first set of row addresses and the second set of row addresses associated with the read command;
receiving data through data input/output pins, according to the column addresses associated with the write command, after a lapse of a predetermined write latency from receiving the write command;
writing the data inputted from the data input/output pins to the at least one of memory cells according to the first set of row addresses and the second set of row addresses associated with the write command; and
outputting the data read from the at least one of memory cells to the data input/output pins, according to the column addresses associated with the read command, after a lapse of a predetermined read latency from receiving the read command.
9. The method according to claim 8 , wherein a timing of using the column addresses is delayed by a predetermined period in comparison with a timing of using the first and second sets of row addresses.
10. The method according to claim 9 , wherein shift registers connected in series are used to generate the delay.
11. The method according to claim 8 , wherein a period of the read latency and a period of the write latency are different from each other.
12. The method according to claim 11 , wherein the period of the read latency is longer than the period of the write latency.
13. The method according to claim 8 , wherein there is a time lag between receiving the data through the data input/output pins and outputting the data read from the at least one of memory cells to the data input/output pins.