Forming interconnect features with reduced sidewall tapering

1. A method, comprising:

forming a stack of materials comprising a first dielectric layer having a conductive feature positioned therein, and a second dielectric layer positioned above said first dielectric layer;

forming an etch mask comprising a plurality of spaced apart mask elements above said second dielectric layer, said mask elements defining at least a first via opening exposing said second dielectric layer;

forming a patterning layer above said etch mask;

forming a second via opening in said patterning layer to expose said first via opening in said etch mask;

etching said second dielectric layer through said second via opening to define a third via opening in said second dielectric layer exposing said conductive feature;

removing said patterning layer and said etch mask; and

forming a conductive via in said third via opening, said conductive via contacting said conductive feature.

2. The method of claim 1 , further comprising:

forming a hard mask layer positioned above said second dielectric layer prior to forming said etch mask, wherein said first via opening exposes a first portion of said hard mask layer;

forming said plurality of spaced apart mask elements to define a first trench opening exposing a second portion of said hard mask layer;

etching said hard mask layer using said etch mask to define a fourth via opening and a second trench opening in said hard mask layer;

forming a sacrificial material in at least said third via opening after etching said second dielectric layer;

removing said patterning layer to expose said second trench opening;

etching said second dielectric layer through said second trench opening to define a trench recess in said second dielectric layer, wherein said sacrificial material at least partially fills said third via opening after said etching;

removing said hard mask layer; and

forming a conductive line in said trench recess.

3. The method of claim 2 , further comprising removing said sacrificial material from said third via opening after defining said trench recess.

4. The method of claim 2 , wherein forming said conductive via and said conductive line comprises:

forming a conductive material above said second dielectric layer and to fill said third via opening and said trench recess; and

removing portions of said conductive material disposed above said second dielectric layer.

5. The method of claim 2 , further comprising removing said patterning layer prior to forming said sacrificial material.

6. The method of claim 1 , further comprising:

forming a hard mask layer positioned above said second dielectric layer prior to forming said etch mask, wherein said first via opening exposes a first portion of said hard mask layer;

etching said hard mask layer using said etch mask to define a fourth via opening in said hard mask layer;

forming a cap layer between said second dielectric layer and said hard mask layer; and

etching said cap layer through said fourth via opening to expose said second dielectric layer.

7. The method of claim 1 , further comprising:

forming a hard mask layer positioned above said second dielectric layer prior to forming said etch mask, wherein said first via opening exposes a first portion of said hard mask layer;

forming said plurality of spaced apart mask elements to define a first trench opening exposing a second portion of said hard mask layer;

etching said hard mask layer using said etch mask to define a fourth via opening and a second trench opening in said hard mask layer;

forming a sacrificial material in at least said third via opening after etching said second dielectric layer; and

removing a first portion of said patterning layer and said sacrificial layer using a planarization process.

8. The method of claim 7 , wherein said patterning layer comprises a first planarization layer, a stop layer formed above said first planarization layer, and a second planarization layer formed above said stop layer, and removing said first portion of said patterning layer and said sacrificial layer comprises removing said second planarization layer and terminating said planarization process on said stop layer.

9. The method of claim 8 , further comprising:

removing said stop layer; and

removing said first planarization layer to expose said second trench opening.

10. The method of claim 9 , further comprising recessing said sacrificial material prior to removing said first planarization layer.

11. The method of claim 7 , further comprising:

forming a cap layer between said second dielectric layer and said hard mask layer;

etching said cap layer through said fourth via opening to expose a first portion of said first dielectric layer; and

etching said cap layer through said second trench opening to expose a second portion of said second dielectric layer.

12. The method of claim 11 , further comprising removing said etch mask and etching said cap layer using a concurrent etching process.

13. The method of claim 2 , further comprising removing said hard mask layer in the presence of said sacrificial material in said third via opening.

14. A method, comprising:

forming a stack of materials comprising a first dielectric layer having a conductive feature positioned therein, a second dielectric layer positioned above said first dielectric layer, and a hard mask layer positioned above said second dielectric layer;

forming an etch mask comprising a plurality of spaced apart mask elements above said hard mask layer, said mask elements defining at least a first via opening exposing a first portion of said hard mask layer and a first trench opening exposing a second portion of said hard mask layer;

etching said hard mask layer using said etch mask to define a second via opening and a second trench opening in said hard mask layer;

forming a patterning layer above said hard mask layer and said mask elements;

forming a third via opening in said patterning layer to expose said second via opening in said hard mask layer;

etching said second dielectric layer through said second via opening to define a fourth via opening in said second dielectric layer exposing said conductive feature;

forming a sacrificial material in at least said fourth via opening;

removing said patterning layer to expose said second trench opening;

etching said second dielectric layer through said second trench opening to define a trench recess in said second dielectric layer, wherein said sacrificial material at least partially fills said fourth via opening during said etching of said second dielectric layer through said second trench opening;

removing said mask elements, said hard mask layer, and said sacrificial material; and

forming a conductive via in said fourth via opening and a conductive line in said trench recess, said conductive via contacting said conductive feature.

15. The method of claim 14 , wherein forming said conductive via and said conductive line comprises:

forming a conductive material above said second dielectric layer and to fill said fourth via opening and said trench recess; and

removing portions of said conductive material disposed above said second dielectric layer.

16. The method of claim 14 , further comprising removing said patterning layer prior to forming said sacrificial material.

17. The method of claim 14 , further comprising removing a first portion of said patterning layer and said sacrificial layer using a planarization process.

18. The method of claim 17 , wherein said patterning layer comprises a first planarization layer, a stop layer formed above said first planarization layer, and a second planarization layer formed above said stop layer, and removing said first portion of said patterning layer and said sacrificial layer comprises removing said second planarization layer and terminating said planarization process on said stop layer.

19. The method of claim 18 , further comprising:

removing said stop layer; and

removing said first planarization layer to expose said second trench opening.

20. The method of claim 19 , further comprising recessing said sacrificial material prior to removing said first planarization layer.